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| October 19, 2001 ISD-300A1 ISD-300A1 High Speed USB to ATA ASIC Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Oct 19, 2001 October 19, 2001 ISD-300A1 Table of Contents TABLE OF CONTENTS .............................................................................................................................. I TABLE OF TABLES .................................................................................................................................III TABLE OF FIGURES ............................................................................................................................... IV DOCUMENT REVISION HISTORY ........................................................................................................ 1 PIN INFORMATION .................................................................................................................................. 2 OVERVIEW ................................................................................................................................................. 6 INTRODUCTION ........................................................................................................................................ 7 ISD-300A1 CONFIGURATION ................................................................................................................. 7 ISD-300A1 CONFIGURATION AND USB DESCRIPTOR SOURCES ................................................................. 7 Internal ROM Contents .......................................................................................................................... 8 I2C Memory Device Interface................................................................................................................. 8 Vendor-Specific Identify Data (FBh) ..................................................................................................... 9 ISD-300A1 CONFIGURATION/USB DESCRIPTOR DATA FORMATTING........................................................ 9 ISD-300A1 Configuration Data.............................................................................................................. 9 USB INTERFACE...................................................................................................................................... 14 DESCRIPTORS ............................................................................................................................................ 14 Supported Descriptors .......................................................................................................................... 14 Descriptor Data Format ........................................................................................................................ 15 DESCRIPTOR REQUIREMENTS .................................................................................................................... 21 String Descriptor Indexes ..................................................................................................................... 21 PIPES ......................................................................................................................................................... 21 Default Control Pipe............................................................................................................................. 21 Bulk Out Pipe ....................................................................................................................................... 21 Bulk In Pipe.......................................................................................................................................... 22 Interrupt Pipe........................................................................................................................................ 22 REQUESTS ................................................................................................................................................. 22 Standard Requests ................................................................................................................................ 22 Mass Storage Class Bulk-Only Requests.............................................................................................. 22 Vendor-Specific Requests .................................................................................................................... 23 ATA/ATAPI INTERFACE........................................................................................................................ 28 PROTOCOL................................................................................................................................................. 28 RESET MAPPING........................................................................................................................................ 28 DEVICE REQUIREMENTS............................................................................................................................ 28 ATA INITIALIZATION TIMEOUT ................................................................................................................ 29 ATA COMMAND BLOCK ........................................................................................................................... 30 Field Descriptions................................................................................................................................. 30 ATA COMMAND FLOW ............................................................................................................................. 33 VENDOR-SPECIFIC ATA COMMANDS........................................................................................................ 35 IDENTIFY............................................................................................................................................ 35 EVENT_NOTIFY ................................................................................................................................ 36 Notification Register Reads.................................................................................................................. 37 i October 19, 2001 ISD-300A1 POWER MANAGEMENT........................................................................................................................ 38 CONTROL PINS .......................................................................................................................................... 38 VBUS_POWERED Pin........................................................................................................................ 38 DRV_PWR_VALID Pin ...................................................................................................................... 39 VBUS_PWR_VALID Pin .................................................................................................................... 39 DISK_READY Pin............................................................................................................................... 39 NLOWPWR Pin ................................................................................................................................... 39 NPWR500 Pin ...................................................................................................................................... 39 ATA INTERFACE LINE STATES.................................................................................................................. 40 OPERATION CONTROL......................................................................................................................... 41 NEJECT, NCART_DET PINS - USB REMOTE WAKEUP AND EVENT NOTIFICATION.............................. 41 GPIO PINS - GENERAL PURPOSE IO ......................................................................................................... 41 I_MODE PIN - VENDOR SPECIFIC IDENTIFY (FBH) ATA COMMAND (I_MODE).................................... 41 SYS_IRQ PIN - USB INTERRUPT ............................................................................................................. 41 ATA_EN PIN - ATA INTERFACE DISABLED ............................................................................................ 42 ATA_PU_EN PIN - ATA INTERFACE PULL-UP RESISTOR SOURCE.......................................................... 42 ATA_PD_EN PIN - ATA INTERFACE PULL-DOWN RESISTOR SINK......................................................... 42 TEST<3:0> PINS - TEST MODES............................................................................................................... 43 XCVR Mux-out Mode.......................................................................................................................... 43 Limbo Mode ......................................................................................................................................... 44 Input NandTree Mode .......................................................................................................................... 44 Bi-di NandTree Mode........................................................................................................................... 44 MANUFACTURING TEST MODE.................................................................................................................. 45 EXTERNAL CIRCUITRY........................................................................................................................ 45 ATA INTERFACE CONSIDERATIONS .......................................................................................................... 45 1K Ohm Pull-down Resistor On DD<7>.............................................................................................. 45 ATA_PD_EN and ATA_PU_EN Usage In Self Powered Systems ..................................................... 45 ATA Interface Termination .................................................................................................................. 46 3.3V Power Regulation ........................................................................................................................ 46 VBUS POWERED SYSTEM CONSIDERATIONS ............................................................................................ 46 GPIO Internal Pull Down Resistors...................................................................................................... 46 ABSOLUTE MAXIMUM RATINGS....................................................................................................... 46 ELECTRICAL CHARACTERISTICS .................................................................................................... 47 VOLTAGE PARAMETER.............................................................................................................................. 47 OPERATION CURRENT PARAMETERS - TYPICAL........................................................................................ 47 TIMING CHARACTERISTICS............................................................................................................... 48 I2C MEMORY DEVICE INTERFACE TIMING ................................................................................................ 48 SYS_IRQ INTERFACE TIMING .................................................................................................................. 49 ATA/ATAPI PORT TIMING CHARACTERISTICS ........................................................................................ 49 CLOCK....................................................................................................................................................... 49 RESET........................................................................................................................................................ 49 PHYSICAL DIAGRAMS .......................................................................................................................... 50 APPENDIX A - EXAMPLE EEPROM OR FBH IDENTIFY DATA CONTENTS............................ 51 ii October 19, 2001 ISD-300A1 Table of Tables Table 1 -Document Revision History ............................................................................................................ 1 Table 2 - Pin Descriptions ............................................................................................................................. 5 Table 3 - ISD-300A1 Configuration and Descriptor Sources ........................................................................ 8 Table 4 - ISD-300A1 Configuration Bytes .................................................................................................. 14 Table 5 - Device Descriptor......................................................................................................................... 16 Table 6 - Device Qualifier Descriptor.......................................................................................................... 16 Table 7 - Standard Configuration Descriptor(s)........................................................................................... 17 Table 8 - Other Speed Configuration Descriptor(s) ..................................................................................... 18 Table 9 - HS and FS Interface Descriptor(s)................................................................................................ 19 Table 10 - String Descriptors....................................................................................................................... 21 Table 11 - Mass Storage Class Bulk-Only Requests ................................................................................... 22 Table 12 - Vendor-Specific Requests .......................................................................................................... 23 Table 13 - LOAD_MFG_DATA Data Block Bit Map ................................................................................ 26 Table 14 - READ_MFG_DATA Data Block Bit Map ................................................................................ 27 Table 15 - ATA Command Block Formatting ............................................................................................. 30 Table 16 - Vendor-Specific ATA Commands ............................................................................................. 35 Table 17 - Identification Register Writes ..................................................................................................... 35 Table 18 - Identification Register Reads ...................................................................................................... 35 Table 19 - Event Notify ATA Command..................................................................................................... 36 Table 20 - Event Notify Drive Status ........................................................................................................... 37 Table 21 - ATA Interface Line States.......................................................................................................... 40 Table 22 - USB Interrupt Pipe Data............................................................................................................. 41 Table 23 - Test Modes ................................................................................................................................. 43 Table 24 - Absolute Maximum Ratings ....................................................................................................... 46 Table 25 - Voltage Characteristics............................................................................................................... 47 Table 26 - Power Supply Current Characteristics........................................................................................ 47 Table 27 - I2C Memory Device Interface Timing ........................................................................................ 48 Table 28 - SYS_IRQ Interface Timing ........................................................................................................ 49 Table 29 - Clock Requirements ................................................................................................................... 49 Table 30 - Example I2C memory device / FBh Identify Data ...................................................................... 62 iii October 19, 2001 ISD-300A1 Table of Figures Figure 1 - Pin Layout ..................................................................................................................................... 2 Figure 2 - ATA Reset Protocol .................................................................................................................... 29 Figure 3- ATA Command Block Flow Diagram ......................................................................................... 34 Figure 4 - SYS_IRQ - USB Interrupt Pipe.................................................................................................. 42 Figure 5 - External Components connection................................................................................................ 45 Figure 6 - I2C Memory Device Interface Timing......................................................................................... 48 Figure 7 - SYS_IRQ Interface Timing......................................................................................................... 49 Figure 8 - Package Outline Diagram............................................................................................................ 50 iv October 19, 2001 ISD-300A1 Document Revision History Title Company Initial Revision # Creation Date/Time Revision 0.8 0.82 0.83 0.9 1.0 1.01 1.02 ISD-300A1 ASIC Datasheet Cypress Semiconductor 0.8 January 16, 2001 Comments Initial revision Grammar edits. Identified I2C limitations Rolled version to release draft Minor corrections, rolled to final release draft. Added text to Figure 5 noting 45 impedance on D+ and D- for High-speed operation. Initial conversion to Cypress document Date January 16, 2001 March 28, 2001 April 18, 2001 June 19, 2001 July 10, 2001 Aug 1, 2001 October 19, 2001 Table 1 -Document Revision History 1 October 19, 2001 ISD-300A1 Pin Information ATA_PD_EN ATA_PU_EN NLOWPWR NDMACK DMARQ NDIOW NDIOR IORDY TMC2 TMC1 NCS0 NCS1 DD13 DD14 DD15 VDD VDD VSS DD2 DD12 DD3 DD11 DD4 DD10 VDD DD5 VSS DD9 DD6 DD8 DD7 NATA_RESET VDD NPWR500 VSS NLED1 NLED0 SDA SCL SYS_IRQ DISK_READY VSS 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 VDD DRV_PWR_VALID 3 VBUS_POWERED 4 BUS_PWR_VALID 5 VSS 6 RREF 7 AVSS 8 AVDD 49 48 47 46 45 44 43 42 41 40 39 VDD VSS VSS DD1 DD0 DA1 DA0 DA2 VSS GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 VDD GPIO3 VSS GPIO2 GPIO1 GPIO0 NCART_DET NEJECT NRESET I_MODE ATA_EN VDD XO XI VSS TEST3 TEST2 VSS ISD-300A 38 37 36 35 34 33 32 31 30 29 28 27 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCAN_EN PVDD RPU VDD VDD AVSS PVSS RSDP RSDM TEST0 TEST1 VDD VSS VSS VSS DP DM Figure 1 - Pin Layout 2 October 19, 2001 ISD-300A1 Pin Name NRESET TQFP Pin # 35 Dir I Type LVTTL, 5V tolerant, hysteresis OSC input OSC output LVTTL, 5V tolerant, internal pull-down resistor LVTTL, 5V tolerant, internal pull-down resistor LVTTL, 5V tolerant, hysteresis Description Active low. Asynchronous chip reset. To evoke reset, NRESET must be held asserted for a minimum of 1 ms after power is stable. 30 MHz crystal connection. 3.3V tolerant input. 30 MHz crystal connection. Active high. ASIC fabrication and mfg. test mode select. The TEST pins must be a noconnect or set to 0x0 during normal operation. Active high. ASIC test - scan chain enable. SCAN_EN must be a no-connect or set to 0 during normal operation. Active high. ATA interface enable. Allows ATA bus sharing with other host devices. Setting ATA_EN=1 enables the ATA interface for normal operation. Disabling ATA_EN 3states (high-Z) the ATA interface and halts the ATA interface state machine logic. Active high. USB interrupt. SYS_IRQ controls ISD-300A1 responses to USB interrupt pipe requests. Setting SYS_IRQ = 1 enables the return of interrupt data to the host. Active high. Indicates device is powered and ready to begin accepting ATA / ATAPI commands. Active low. Indicates when the ISD-300A1 is in a low power state of operation. Open drain during normal operation. Active low. Indicates the USB host has enabled use of VBUS power (USB configuration set to 1) up to the requested amount in the USB descriptor bMaxPower entry. VBUS powered devices must condition power circuitry with the state of the VBUS_POWERED signal for correct operation. Open drain during normal operation. Active high. Indicates the amount of VBUS current the system is capable of consuming (typically <= 100 mA OR <= 500 mA) Active high. Indicates that VBUS power is present. Power / connection indication in hybrid power systems (VBUS ISD-300A1, brick device). Functionality and active polarity is controlled with configuration data. Set DRV_PWR_VALID = 0 if the functionality is not utilized. General purpose IO pins. Configuration data provides independent 3-state control for each GPIO pin. The GPIO pins may be left as noconnect if functionality is not utilized. Active low. Media present indication. If remote wakeup is enabled by the USB host, a state change on this pin will cause the ISD-300A1 to perform a USB remote wakeup event. Filtered internally by ISD-300A1. Set NCART_DET = 1 if the functionality is not utilized. XI XO TEST0 - TEST3 30 31 23, 24, 27, 28 I O I SCAN_EN 22 I ATA_EN 33 I SYS_IRQ 98 I LVTTL, 5V tolerant, internal pull down resistor, hysteresis LVTTL, 5V tolerant, hysteresis 12 mA LVTTL, 5V tolerant 12 mA LVTTL, 5V tolerant DISK_READY 99 I NLOWPWR 52 O NPWR500 92 O VBUS_POWERED 3 I LVTTL, 5V tolerant, hysteresis LVTTL, 5V tolerant, hysteresis LVTTL, 5V tolerant, hysteresis VBUS_PWR_VALID 4 I DRV_PWR_VALID 2 I GPIO0 - GPIO9 38, 39, 40, 42, 44, 45, 46, 47, 48, 49 IO 12 mA LVTTL, 5V tolerant, internal pulldown resistor LVTTL, 5V tolerant, hysteresis NCART_DET 37 I 3 October 19, 2001 ISD-300A1 Pin Name NEJECT TQFP Pin # 36 Dir I Type LVTTL, 5V tolerant, hysteresis Description Active low. Media eject requested. If remote wakeup is enabled by the USB host, a state change on this pin will cause the ISD-300A1 to perform a USB remote wakeup event. Filtered internally by ISD-300A1. Set NEJECT = 1 if the functionality is not utilized. I2C clock. Open drain during normal operation. This pin may be left as a no-connect pin if the I2C interface is not utilized. I2C address/data. Open drain during normal operation. An external pull-up resistor is required for correct operation in all ISD-300A1 modes of operation. ATA control. ATA control. ATA Address. ATA Data. SCL 97 O 6 mA LVTTL, 5V tolerant SDA 96 IO 6 mA LVTTL, 5V tolerant DMARQ NDMACK DA0 - DA2 DD0 - DD15 69 61 56, 59, 55 71, 73, 77, 79, 81, 84, 87, 89, 88, 86, 82, 80, 78, 74, 72, 70 64 65 54, 53 63 62 I O O IO LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe NDIOR NDIOW NCS0, NCS1 IORDY ATA_PU_EN O O O I O 6 mA LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe ATA control. ATA control. ATA Chip Selects. ATA control. Active high. ATA IORDY pull-up connection. Driven low during USB suspend, 3-stated (hi-Z) when ATA_EN=0. Active low. ATA DMARQ pull-down connection. 3-state (hi-Z) when ATA_EN=0. Active low. ATA reset. Active low. LED drive to indicate USB bus speed. Active when utilizing HS, inactive during FS or USB suspend or other low power modes of operation. Open drain during normal operation. Leave as a no-connect pin if functionality is not utilized. Active low. LED drive to indicate status of device initialization. Flashing when initializing is in progress, solid when the device is initialized, and inactive during USB suspend or other low power modes of operation. Open drain during normal modes of operation. Leave as a noconnect pin if functionality is not utilized. Active high. Indicates ISD-300A1 configuration / USB descriptor information is obtained using the ATA vendor specific Identify command (FBh) USB full speed output buffer (D-). RSDM also functions as a current sink for termination during HS operation. ATA_PD_EN NATA_RESET NLED0 67 90 95 O O O 6 mA LVTTL, 5V Fail Safe 6 mA LVTTL, 5V Fail Safe 12 mA LVTTL NLED1 94 O 12 mA LVTTL I_MODE 34 I LVTTL, 5V Tolerant USB IO RSDM 16 O 4 October 19, 2001 ISD-300A1 Pin Name DM DP RSDP TQFP Pin # 15 13 12 Dir IO IO O Type USB IO USB IO USB IO Description USB high speed IO buffer (D-). USB high speed IO buffer (D+). USB full speed output buffer (D+). RSDP also functions as a current sink for termination during HS operation. RPU sources power for the 1.5K ohm resistor attached to D+ during full speed operation. PLL voltage reference. Current source for 9.1K ohm resistor (1%) connected to AVSS. Fabrication only. Connect to VSS. Fabrication only. Connect to VSS. Analog 3.3V supply (PLL) Analog 3.3V ground (PLL) Analog 3.3V supply Analog ground 3.3V digital supply Digital ground RPU RREF TMC1 TMC2 PVDD PVSS AVDD AVSS VDD VSS 10 6 57 60 19 18 8 7, 9 1, 14, 21, 25, 32, 43, 51, 68, 75, 83, 91 5, 11, 17, 20, 26, 29, 41, 50, 58, 66, 76, 85, 93, 100 O USB output Analog I I ASIC test ASIC test Table 2 - Pin Descriptions 5 October 19, 2001 ISD-300A1 Overview * * * * * Compact 100 pin TQFP package - No Requirement For Additional External ROM Or RAM USB Mass Storage Class Bulk-Only Specification Compliant (Version 1.0) 5V Tolerant Inputs, 3.3V Output Drive, Single 3.3V Supply Voltage Requirement Simplifies System Integration Command Queuing Hooks In Hardware Allow Near Theoretical USB Data Transfer Rates USB Version 2.0 Compliant * * * * Integrated USB Transceiver High Speed (480 Mbit) And Full Speed (12 Mbit) Support USB Suspend / Resume, Remote Wakeup Support Two Power Modes Of Operation USB Bus Powered Self Powered I2C Serial ROM Interface ATA Interface Using Vendor Specific ATA Command (FBh) Implemented On ATAPI Or ATA Device Default On-Chip ROM Contents For Manufacturing / Development Flexible USB Descriptor And Configuration Retrieval Source Large 8 Kbyte Data Buffer Maximizes ATA / ATAPI Data Transfer Rate ATA Interface Supports ATA PIO Modes 0-4, UDMA Modes 0-4 Of Operation (Multi-word DMA Not Supported). ATA Interface Operation Mode Is Automatically Selected During Device Initialization Or Manually Programmed With Configuration Data Automatic Detection Of Either Master or Slave ATA/ATAPI Devices Event Notification Via Vendor Specific ATA Command Configurable ATA Command Input Pins For Media Cartridge Detection And Ejection Request USB Bus State Indications (Reset, FS/HS Mode Of Operation, Suspend/Resume) * * * * Multiple LUN support ATA Translation Provides Seamless ATA Support with Standard MSC Drivers Additional ATA Command Support Provided By Vendor Specific ATACBs (ATA Command Blocks Utilizing the MSC Command Block Wrapper) * * * Provisions To Share ATA Bus With Other Hosts Manufacturing Interconnect Test Support Provided With Vendor Specific USB Commands Read / Write Access To Relevant ASIC Pins Utilizes Inexpensive 30Mhz Crystal For Clock Source 6 October 19, 2001 ISD-300A1 Introduction The ISD-300A1 implements a bridge between one USB port and one ATA or ATAPI based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport specification. Hardware design allows CBW command queuing, which with vendor specific drivers allows data transfer rates of up to the USB theoretical maximum. The USB port of the ISD-300A1 is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the ISD-300A1 and receives status and data from the ISD-300A1 using standard USB protocol. The ATA/ATAPI port of the ISD-300A1 is connected to a mass storage device. A large 8 Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0-4, and Ultra Mode DMA modes 0-4. The device initialization process is configurable, enabling the ISD-300A1 to initialize most ATA/ATAPI devices without software intervention. The ISD-300A1 can also be configured to allow software initialization of a device if initialization requirements are not supported by ISD-300A1 algorithms. ISD-300A1 Configuration Certain timing parameters and operational modes are configurable by external configuration data. USB descriptor information is also retrieved externally. ISD-300A1 configuration data should not be confused with the USB Configuration Descriptor data. ISD-300A1 Configuration and USB Descriptor Sources ISD-300A1 configuration and USB descriptor data can be retrieved from three sources. Table 3 indicates the method of determining which data source is used. ISD-300A1 configuration and USB descriptor data can be supplied from an I2C serial memory device. The ISD-300A1 can address 2 Kbytes of I2C data, but ISD-300A1 configuration and USB descriptor information are limited to 512 bytes maximum. Unused register space in the I2C serial memory device may be used for product specific data storage. Note that no descriptor is allowed to span multiple pages within the I2C serial memory device. The ISD-300A1 provides support for the 24LC01-16 EEPROM family. Alternatively, configuration and descriptor data can be supplied by an attached mass storage device through a vendor-specific Identify (FBh) ATA command. The ISD-300A1 provides 256 bytes of internal RAM for FBh data storage. The ISD-300A1 also contains an internal set of ISD-300A1 configuration and USB descriptors. Retrieval of internal ROM data will occur under the specific circumstances outlined in Table 3. The internal descriptors may only be used during manufacturing, as the internal ROM values disable some features required for normal operation to aid use in a manufacturing environment. NOTE: The internal descriptors do not provide a unique serial number (required for USB Mass Storage Class compliance), and therefore cannot be used for shipping products. An external I2C memory device or utilization of the vendor specific FBh identify command is required to correctly configure the ISD-300A1 for operation and provide a unique serial number for MSC compliance. 7 October 19, 2001 ISD-300A1 Table 3 describes how the ISD-300A1 determines USB descriptor / configuration sources. I_MODE Pin Active No I2C Memory Device present No Signature Check Passes X ISD-300A1 Configuration and USB Descriptor Retrieval Yes Yes X X No Yes No Yes No No Yes Yes In this mode, the ISD-300A1 uses internal ROM contents for USB descriptor information and configuration register values. This mode is for debug / manufacturing operation only. Not for shipping products. In this mode, the ISD-300A1 uses internal ROM contents for USB descriptor information. Configuration register values are loaded from internal ROM. This is not a valid mode of operation. The ISD-300A1 retrieves all Descriptor and Configuration values from the vendor-specific Identify (FBh) data. The ISD-300A1 is configured using internal ROM values until FBh data becomes available. The ISD-300A1 uses internal ROM contents for USB descriptor information. Configuration register values are loaded from internal ROM. In this mode of operation, any ISD-300A1 vendor specific configuration access causes the ISD-300A1 to recheck the signature field. Once the signature check passes, SROM data is returned for USB descriptors requests. This is not a valid mode of operation. The ISD-300A1 retrieves all Descriptor and Configuration values from the I2C memory device. The ISD-300A1 is configured using values present in the I2C memory device data. Table 3 - ISD-300A1 Configuration and Descriptor Sources Internal ROM Contents Internal on-board ROM addresses and the contents of those locations are shown in the ISD-300A1 Configuration/USB Descriptor Data Formatting section on page 9 of this document. Internal ROM is necessary for manufacturing activities. Internal ROM contents allow the host to enumerate the ISD-300A1 when an un-programmed I2C memory device is connected. I2C Memory Device Interface The ISD-300A1 supports a subset of the "slow mode" specification (100 KHz) required for 24LC01-16 EEPROM family device support. Features such as "Multi-Master", "Clock Synchronization" (the SCL pin is output only), "10-bit addressing", and "CBUS device support", are NOT supported. Vendor specific USB commands allow the ISD-300A1 to address up to 2 K bytes of data (although configuration / descriptor information is limited to 512 bytes of register space). Following release of NRESET, the ISD-300A1 waits 50ms, then checks for I2C device presence. If an I2C device is present but does not pass signature check (first two data bytes must equal 0x4D54), the ISD300A1 re-tests the signature with each vendor specific USB load or read access of configuration bytes 0 and 1. Once the signature check passes, I2C data is returned for USB descriptor requests. If an I2C device is detected initially, it is always assumed present until the next reset cycle (NRESET). If an I2C device is present, a lack of an ACK response when required causes the ISD-300A1 to stall that USB request. The ISD-300A1 will attempt the access again with the next USB request. Programming of the I2C memory device can be accomplished using an external device programmer, ISD300A1 supported vendor specific USB commands, or using a "bed of nails". An example of I2C memory device data formatting is shown in Appendix A - Example EEPROM or FBh Identify Data Contents. 8 October 19, 2001 ISD-300A1 Vendor-Specific Identify Data (FBh) If an I2C memory device is not utilized, the ISD-300A1 must be configured to accept descriptor and configuration data from an attached device using a vendor-specific identify command. (See I_MODE Pin on page 41) For vendor specific identify data (FBh) to be deemed valid, it must pass the signature check (first two data bytes must equal 0x4D54). In the event of a failed signature check, the ISD-300A1 will respond to all USB GET_DESCRIPTOR or GET_CONFIGURATION commands by returning defaults contained in internal ROM. An example of vendor specific identify data (FBh) formatting is shown in Appendix A - Example EEPROM or FBh Identify Data Contents on page 51. ISD-300A1 Configuration/USB Descriptor Data Formatting Data formatting for all ISD-300A1 configuration data and USB descriptor data is identical for internal ROM, I2C memory device data, and vendor specific identify data (FBh). The following sections show how the ISD-300A1 configuration data is mapped into address space. The USB Interface section on page 14 explains formatting of USB descriptor data. ISD-300A1 Configuration Data The ISD-300A1 Configuration Data is located at addresses 0x0 to 0xF of the Descriptor/Configuration data contents. Configuration Data determine certain parameters and operational modes used by the ISD-300A1. Any vendor specific USB command write operation to I2C memory device configuration space will simultaneously update internal configuration register values as well. If the I2C memory device is programmed without vendor specific USB commands, the ISD-300A1 must be asynchronously reset (NRESET) before configuration data is reloaded. Formatting is identical for the internal ROM, the I2C memory device, and FBh data. ISD-300A1 configuration data is loaded into internal registers, regardless of the original data source. Address 0x0 0x1 0x2 0x3 Field Name I2C memory device Signature (LSB) I2C memory device Signature (MSB) Event Notification APM Value Description LSB I2C memory device signature byte. Register does not exist in HW MSB I2C memory device signature byte. Register does not exist in HW ATAPI event notification command. Setting this field to 0x00 disables this feature. ATA Device Automatic Power Management Value. If an attached ATA device supports APM and this field contains other than 0x00, the Initialization state machines will issue a SET FEATURES command to Enable APM with the register value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This register value is ignored with ATAPI devices. Time in 128 millisecond granularity before the ISD-300A1 stops polling the ALT STAT register for reset complete and restarts the reset process (0x80 = 16.4 seconds). On-board ROM Defaults 0x54 0x4D 0x00 0x00 0x4 ATA Initialization Timeout 0x80 9 October 19, 2001 ISD-300A1 Address 0x5 Field Name USB Bus Mode Description Bit (7) - read only. USB bus mode of operation 0 USB bus is operating in full speed mode (12 Mbit/sec). 1 USB bus is operating in high speed mode (480 Mbit/sec). Bit (6) CBW Command Block Size. 0 12 byte ATAPI CB 1 16 byte ATAPI CB Bit (5) Device number selection. This bit is valid only when "Skip ATA/ATAPI Device Initialization" is active. Under ISD-300A1 control ("Skip ATA/ATAPI Device Initialization = `0'), the value is ignored. 0 Drive 0 (master) 1 Drive 1 (slave) Bit (4) ATAPI reset during drive initialization. Setting this bit enables the ATAPI reset algorithm in the drive initialization state machines Bit (3) - read only. Indicates if an ATA or ATAPI device is detected 0 ATAPI device 1 ATA device or possible device initialization failure. Bit(2) Force USB full speed only operation. Setting this bit prevents the ISD-300A1 from negotiating HS operation during USB reset events 0 Normal operation - allow HS negotiation during USB reset 1 USB FS only - do not allow HS negotiation during USB reset Bit(1) Vendor Specific / MSC SOFT_RESET control. 0 Vendor Specific USB command utilized for SOFT_RESET 1 Mass Storage Class USB command utilized for SOFT_RESET Bit (0) DISK_READY active polarity. DISK_READY Polarity is ignored if I_MODE is set to 1. During I_MODE operation DISK_READY polarity is active high. 0 Active high polarity 1 Active low polarity Value in CBW CB field that designates if the CB is decoded as vendor specific ATA commands instead of the ATAPI command block. Value in CBW CB field that designates if the CB is decoded as vendor specific ATA commands instead of the ATAPI command block. On-board ROM Defaults 0x00 ATAPI Command Block Size Master/Slave Selection ATAPI Reset ATA_NATAPI Force USB FS VS / MSC SOFT_RESET DISK_READY Polarity 0x6 0x7 ATA Command Designator (Byte 0, LSB) ATA Command Designator (Byte 1, MSB) 0x24 0x24 10 October 19, 2001 ISD-300A1 Address 0x8 Field Name Initialization Status Description Bit (7) - read only Drive Initialization Status If set, indicates the drive initialization sequence state machine is active Bit (6) Allows software to manually enable ATA Translation with devices that do not support ISD-300A1 device initialization algorithms. Note: Force ATA Device must be set'1' in conjunction with Skip ATA/ATAPI Device Initialization and ATA Translation Enable. Software must issue an INQUIRY command followed with a MSC reset to allow the ISD-300A1 to parse drive information and optimize system performance and operation. Force ATA Device should be set `0' for devices that support ISD-300A1 device initialization algorithms. Bit (5) Skip_Init - This bit should be cleared for I_MODE operation. The host driver must initialize the attached device (if required) when this bit is set. Note:For ATAPI devices, if Skip_Init is set the host driver must issue an IDENTIFY command utilizing ATACBs to allow the ISD-300A1 to parse drive information and optimize system performance and operation. Refer to bmATACBActionSelect in the ATA Command Block - Field Descriptions section on page 30 for further information. 0 normal operation 1 only reset the device and write the device control register prior to processing commands. Bit (4:3) - Shall be set to `0' Bits (2:0) Maximum number of LUNs device supports. Bits (7) - read only. Current logic state of the ATA_EN pin Bit (6:1) - Shall be set to 0 Bit (0) SRST reset during drive initialization. Setting this bit enables the SRST reset algorithm in the drive initialization state machines. Bits (7:4) Standard values for ATA compliant devices and a 30.0 MHz system clock (in binary). Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 0101 (5+1)*33.33 = 200 ns mode 1 0011 (3+1)*33.33 = 133 ns mode 2 0011 (3+1)*33.33 = 133 ns mode 3 0010 (2+1)*33.33 = 100 ns mode 4 0010 (2+1)*33.33 = 100 ns Bits (3:0) ATA cycle times are calculated using Data Assert and Data Recover values. Standard recover values and cycle times for ATA compliant devices and a 30.0 MHz system clock (in binary). Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 1100 (4+1)+(12+1)*33.33 = 600 ns mode 1 0111 (3+1)+(7+1)*33.33 = 400 ns mode 2 0011 (2+1)+(3+1)*33.33 = 233 ns mode 3 0010 (2+1)+(2+1)*33.33 = 200 ns mode 4 0000 (2+1)+(0+1)*33.33 = 133 ns On-board ROM Defaults 0x00 Force ATA Device Skip ATA / ATAPI Device Initialization Obsolete Last LUN Identifier 0x9 ATA_EN Obsolete SRST Enable 0xA ATA Data Assert 0x01 0x5C ATA Data Recover 11 October 19, 2001 ISD-300A1 Address 0xB Field Name ATA Data Setup Description Bits (7:5) Setup time is only incurred on the first data cycle of a burst. Standard values for ATA compliant devices and a 30.0 MHz system clock are (in binary): Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 010 (2+1)*33.33 = 133 ns mode 1 001 (1+1)*33.33 = 66 ns mode 2 001 (1+1)*33.33 = 66 ns mode 3 001 (1+1)*33.33 = 66 ns mode 4 000 (0+1)*33.33 = 33 ns Bit (4) Controls the polarity of DRV_PWR_VALID pin 0 Active low ("connector ground" indication) 1 Active high (power indication from device) Bit (3) This field is used in conjunction with ATA Data Setup, ATA Data Assertion, ATA Data Recover, and PIO Mode Selection fields. 0 Use timing information acquired from the Drive 1 Override device timing information with configuration values Bit (2) Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be enabled in cable applications where the ISD-300A1 is VBUS powered. 0 pin disabled (most systems) 1 pin enabled Bit(1) PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data bus during PIO read operations while addressing the data register. In most applications this bit is set to `0'. This functionality is provided as a solution for devices that erroneously drive the ATA data bus continuously during PIO data register reads. 0 Normal operation as per ATA/ATAPI interface specification. 1 3-state (hi-Z) DD[15:0] during PIO data register reads. Bit (0) - read only This bit reflects the current state of the I_MODE input pin. On-board ROM Defaults 0x40 Drive Power Valid Polarity Override PIO Timing Drive Power Valid Enable ATA Read Kludge I_MODE 12 October 19, 2001 ISD-300A1 Address 0xC Field Name SYS_IRQ DISK_READY ATA Translation Enable Description Bits(7) - read only This bit reflects the current logic state of the SYS_IRQ input. Bit(6) - read only This bit reflects the current logic state of the DISK_READY input. Bit(5) Enable ATAPI to ATA protocol translation enable. If enabled, AND if an ATA device is detected, ATA translation is enabled. Note: If Skip ATA/ATAPI Device Initialization is set `1', Force ATA Device must also be set `1' in order to utilize ATA translation. Software must further issue an INQUIRY command followed with an MSC reset to enable ATA translation operation. 0 ATA Translation Disabled 1 ATA Translation Enable Bit(4) Enable Ultra Mode data transfer support for ATA devices. If enabled, AND the ATA device reports UDMA support, the ISD-300A1 will utilize UDMA data transfers. 0 Disable ATA device UDMA support 1 Enable ATA device UDMA support Bit(3) Enable Ultra Mode data transfer support for ATAPI devices. If enabled, AND the ATAPI device reports UDMA support, the ISD-300A1 will utilize UDMA data transfers. 0 Disable ATAPI device UDMA support 1 Enable ATAPI device UDMA support Bits(2:0) ROM UDMA Mode indicates the highest UDMA mode supported by the product. The ISD-300A1 will utilize the lesser of ROM UDMA Mode or the highest mode supported by the device. Note: UDMA read operation mode timing is controlled by the device. mode 0 000 133.3 ns per 16-bit word write mode 1 001 100 ns per 16-bit word write mode 2 010 66.7 ns per 16-bit word write mode 3 011 66.7 ns per 16-bit word write mode 4 100 33.3 ns per 16-bit word write On-board ROM Defaults 0x00 ATA UDMA Enable ATAPI UDMA Enable ROM UDMA Mode 13 October 19, 2001 ISD-300A1 Address 0xD Field Name PIO Mode Selection Description Bits (7:5) PIO Mode Selection. The PIO mode reported back to the device if the Override PIO Timing configuration bit is set. This field represents the PIO mode of operation configured by the ATA Data Setup, ATA Data Assertion, ATA Data Recover, and Override PIO Timing fields. mode 0 000 mode 1 001 mode 2 010 mode 3 011 mode 4 100 Bit (4) Skip ATA_NRESET assertion. Note: SRST Enable must be set in conjunction with Skip Pin Reset. Setting this bit causes the Initialize algorithm to bypass ATA_NRESET assertion unless a DISK_READY 0=>1 event occurred. All other reset events utilize SRST as the drive reset mechanism. 0 Allow ATA_NRESET assertion for all resets 1 Disable ATA_NRESET assertion except for drive power-on reset cycles Bits (3:2) GPIO[9:8] input / output control Writing this register controls the output state of the GPIO pin (if the 3-state control is enabled) Reading this register returns the logic value from the GPIO pin Bits (1:0) GPIO[9:8] 3-state control 0 Output enabled (GPIO pin is an output) 1 3-state(hi-Z) (GPIO pin is an input) Bits(7:0) GPIO[7:0] input / output control Writing this register controls the output state of the GPIO pin (if the 3-state control is enabled) Reading this register returns the logic value from the GPIO pin Bits(7:0) GPIO[7:0] 3-state control 0 Output enabled (GPIO pin is an output) 1 3-state (hi-Z) (GPIO pin is an input) On-board ROM Defaults 0x03 Skip Pin Reset General Purpose IO General Purpose IO 3state control 0xE General Purpose IO 0x00 0xF General Purpose IO 3state control 0xFF Table 4 - ISD-300A1 Configuration Bytes USB Interface The ISD-300A1 is electrically and logically compliant with the Universal Serial Bus Specification Revision 2.0. Descriptors Supported Descriptors * * Device USB Device Qualifier The ISD-300A1 requires only one Device Qualifier descriptor. The information returned is identical for full and high speed modes of operation. 14 October 19, 2001 ISD-300A1 * Standard Configuration The ISD-300A1 supports two configurations, depending on the mode of operation. See the VBUS_POWERED section on page 38 for more information. Configuration bus-powered. This configuration descriptor is reported if the VBUS_POWERED signal is set active, typically indicating more than 100 mA of current is sourced from VBUS. Configuration non-bus-powered. This configuration descriptor is reported if the VBUS_POWERED input is set inactive, indicating the system is sourcing 100 mA or less of current from VBUS (self powered system). Other Speed Configuration The ISD-300A1 supports two configurations, depending on the mode of operation. See the VBUS_POWERED section on page 38 for more information. Other Speed Configuration bus-powered. This configuration descriptor is reported if the VBUS_POWERED signal is active. Other Speed Configuration non-bus-powered. This configuration descriptor is reported if the VBUS_POWERED input is inactive. Interface The ISD-300A1 supports two interface descriptors, both FS (full speed) and HS (high speed), each with four possible endpoints. * Endpoint The ISD-300A1 supports the following endpoints: Default Control endpoint. Accessible as endpoint 0. Bulk Out endpoint. Accessible as endpoint 1. Bulk In endpoint. Accessible as endpoint 2. Interrupt endpoint. Accessible as endpoint 3. * * * String The ISD-300A1 supports a set of class and vendor-specific string descriptors. For more information on strings, refer to the String Descriptors section on page 19 of this document. Descriptor Data Format Device Descriptor There is only one device descriptor for each USB device. This descriptor gives USB information about the ISD-300A1 device such as device class and device subclass, etc. Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C Field Name bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB) Device release number in BCD LSB (product release number) Product ID. Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Vendor ID. Description Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. On-board Defaults 0x12 0x01 0x00 0x02 0xFF 0x00 0xFF 0x40 0xAB 0x05 0x6A 0x00 0x00 15 October 19, 2001 ISD-300A1 Address 0x1D 0x1E 0x1F 0x20 0x21 Field Name bcdDevice (MSB) iManufacturer iProduct iSerialNumber bNumConfigurations Description Device release number in BCD MSB (silicon release number). NOTE: This field entry is always returned from internal ROM contents, regardless of the descriptor source. Index to manufacturer string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Index to product string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Index to serial number string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. The USB Mass Storage Class Bulk Only Transport Specification requires a unique serial number. Number of configurations supported. On-board Defaults 0x10 (300A) 0x11 (300A1) 0x49 0x5A 0x00 0x01 Table 5 - Device Descriptor Device Qualifier Descriptor The device qualifier descriptor describes information about a high-speed capable device that would change if the device were operating at the other speed. For the ISD-300A1, none of the descriptor information requires modification, thus only one Device Qualifier Descriptor is required. The ISD-300A1 returns the same descriptor while operating in either full speed or high speed mode. Address 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B Field Name bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations bReserved Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Number of configurations supported Reserved for future use, must be zero Description Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. On-board Defaults 0x0A 0x06 0x00 0x02 0xFF 0x00 0xFF 0x40 0x01 0x00 Table 6 - Device Qualifier Descriptor Standard Configuration Descriptor The ISD-300A1 requires two configuration descriptors. The first configuration is returned when the VBUS_POWERED signal is active, the second configuration when the VBUS_POWERED signal is inactive (brick powered). The configuration descriptor contains information about the ISD-300A1 device configuration. Each configuration has one interface that supports four endpoints. See the VBUS_POWERED section on page 38 for more information. Address (Config. Number) 0x2C(1) 0x80(2) 0x2D(1) 0x81(2) bLength bDescriptorType Length of configuration descriptor in bytes. Descriptor type. Field Name Description On-board Defaults 0x09 0x02 16 October 19, 2001 ISD-300A1 Address (Config. Number) 0x2E(1) 0x82(2) 0x2F(1) 0x83(2) 0x30(1) 0x84(2) 0x31(1) 0x85(2) 0x32(1) 0x86(2) 0x33(1) 0x87(2) bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to the configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved, set to 1. `1' 6 Self-powered. `0' for configuration 1, `1' for configuration 2 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' Maximum power consumption for this configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Field Name Description On-board Defaults 0x27 0x00 0x01 0x02 0x00 0x80 (1) 0xC0 (2) 0x34(1) 0x88(2) bMaxPower 0xF9 (1) 0x31 (2) Table 7 - Standard Configuration Descriptor(s) Other Speed Configuration Descriptor This descriptor describes a configuration of a high-speed capable device if it were operating at its other possible speed. Although two descriptors are not required to distinguish differences between full speed and high speed operation, the ISD-300A1 supports two other speed configuration descriptors to enumerate differences between VBUS powered and self powered operation. The first configuration is returned when the VBUS_POWERED signal is active, the second configuration when the VBUS_POWERED signal is inactive. Each configuration has one interface that supports four endpoints. See the VBUS_POWERED section on page 38 for more information. Address (Config. Number) 0x35(1) 0x89(2) 0x36(1) 0x8A(2) 0x37(1) 0x8B(2) 0x38(1) 0x8C(2) 0x39(1) 0x8D(2) 0x3A(1) 0x8E(2) 0x3B(1) 0x8F(2) 0x3C(1) 0x90(2) bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved, set to 1. `1' 6 Self-powered. `0' for configuration 1, `1' for configuration 2 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' Maximum power consumption for the second configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Field Name Description On-board Defaults 0x09 0x07 0x27 0x00 0x01 0x02 0x00 0x80 (1) 0xC0 (2) 0x3D(1) 0x91(2) bMaxPower 0xF9 (1) 0x31 (2) 17 October 19, 2001 ISD-300A1 Table 8 - Other Speed Configuration Descriptor(s) Interface Descriptor This descriptor specifies the interface within a configuration. There are two interface descriptors in the ISD-300A1, one for high speed, and one for full speed. Each interface contains four endpoint descriptors: Default Control (no descriptor), Bulk out, Bulk in, and Interrupt. Interface and endpoint descriptors cannot be directly accessed using the Get_Descriptor USB command. However, interface and endpoint descriptors are always returned as part of the configuration and other speed configuration descriptor. When the other speed configuration descriptor is requested, the interface descriptor returned is dependent upon the USB bus speed mode of operation. When operating in high speed, the full speed interface descriptor is returned with the other speed configuration descriptor. When operating in full speed, the high speed interface descriptor is returned with the other speed configuration descriptor. Endpoint descriptors and addresses must be in the fixed order of the ISD-300A1 internal defaults: Bulk-out first, then Bulk-in, followed by Interrupt. Address (HS or FS) Interface Descriptor 0x3E(HS) 0x5D(FS) 0x3F(HS) 0x5E(FS) 0x40(HS) 0x5F(FS) 0x41(HS) 0x60(FS) 0x42(HS) 0x61(FS) 0x43(HS) 0x62(FS) 0x44(HS) 0x63(FS) 0x45(HS) 0x64(FS) 0x46(HS) 0x65(FS) 0x47(HS) 0x66(FS) 0x48(HS) 0x67(FS) 0x49(HS) 0x68(FS) 0x4A(HS) 0x69(FS) 0x4B(HS) 0x6A(FS) 0x4C(HS) 0x6B(FS) 0x4D(HS) 0x6C(FS) 0x4E(HS) 0x6D(FS) bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings Number of endpoints Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. USB Bulk Out Endpoint Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 1. This is a bulk endpoint. Max data transfer size. 0x09 0x04 0x00 0x00 0x03 0xFF 0x00 0xFF 0x00 Field Name Description On-board Defaults bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval 0x07 0x05 0x01 0x02 0x00 (HS) 0x40 (FS) 0x02 (HS) 0x00 (FS) 0x01 (HS) 0x00 (FS) 0x07 HS interval for polling (max NAK rate). Does not apply to FS bulk endpoints. USB Bulk In Endpoint Length of this descriptor in bytes. bLength 18 October 19, 2001 ISD-300A1 Address (HS or FS) 0x4F(HS) 0x6E(FS) 0x50(HS) 0x6F(FS) 0x51(HS) 0x70(FS) 0x52(HS) 0x71(FS) 0x53(HS) 0x72(FS) 0x54(HS) 0x73(FS) 0x55(HS) 0x74(FS) 0x56(HS) 0x75(FS) 0x57(HS) 0x76(FS) 0x58(HS) 0x77(FS) 0x59(HS) 0x78(FS) 0x5A(HS) 0x79(FS) 0x5B(HS) 0x7A(FS) bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval Endpoint descriptor type. This is an In endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. Field Name Description On-board Defaults 0x05 0x82 0x02 0x00 (HS) 0x40 (FS) 0x02 (HS) 0x00 (FS) 0x01 (HS) 0x00 (FS) 0x07 0x05 0x83 0x03 0x02 0x00 HS interval for polling (max NAK rate). Does not apply to FS bulk endpoints. USB Interrupt Endpoint Length of this descriptor in bytes. Endpoint descriptor type. This is an Interrupt endpoint, endpoint number 3. This is an interrupt endpoint. Max data transfer size. bLength bDescriptorType bEndpointAddress BmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval This is the polling interval. 0x05 (HS) 0x20 (FS) Table 9 - HS and FS Interface Descriptor(s) String Descriptors The ISD-300A1 supports multiple string descriptors, such as a manufacturer name string indexed by the iManufacturer field in the Device Descriptor. The descriptor index is specified as the starting address values divided by 2 (i.e. Manufacturer string begins at address 0x92, but is specified in the iManufacturer field as 0x49). String index 0 must contain the LANGID of exactly one language, as the ISD-300A1 supports only a single language. Microsoft defines the LANGID codes for Windows, as described in Developing International Software for Windows 95 and Windows NT, Nadine Kano, Microsoft Press, Redmond, Washington. Note the LANGID code for English is 0x0409. The following table shows how the LANGID, manufacturer, and product strings are formatted in the on-board ROM contents, and this can be considered an example of how to format strings in the I2C memory device or FBh Identify data. Each string character is comprised of an ASCII character appended to a NULL byte to meet the UNICODE encoding requirements as specified in The Unicode Standard, Worldwide Character Encoding, Version 1.0, Volumes 1 and 2. Address Field Name Description USB String Descriptor - Index 0 (LANGID) 0x7C 0x7D 0x7E 0x7F bLength bDescriptorType LANGID (LSB) LANGID (MSB) LANGID string descriptor length in bytes. Descriptor type. Language supported. Note: See LANGID table in Microsoft documentation (the code for English is 0x0409) USB String Descriptor - Manufacturer 0x04 0x03 0x09 0x04 On-board Defaults 19 October 19, 2001 ISD-300A1 Address 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 Field Name bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString String descriptor length in bytes Descriptor type. ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") USB String Descriptor - Product String descriptor length in bytes Descriptor type ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") 0x28 0x03 0x55 ("U") 0x00 0x53 ("S") 0x00 0x42 ("B") 0x00 0x20 (" ") 0x00 0x53 ("S") 0x00 0x74 ("t") 0x00 Description On-board Defaults 0x22 0x03 0x49 ("I") 0x00 0x6E ("n") 0x00 0x2D ("-") 0x00 0x53 ("S") 0x00 0x79 ("y") 0x00 0x73 ("s") 0x00 0x74 ("t") 0x00 0x65 ("e") 0x00 0x6D ("m") 0x00 0x20 (" ") 0x00 0x44 ("D") 0x00 0x65 ("e") 0x00 0x73 ("s") 0x00 0x69 ("i") 0x00 0x67 ("g") 0x00 0x6E ("n") 0x00 20 October 19, 2001 ISD-300A1 Address 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xFF Field Name bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString Unused ROM space ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") ASCII character. ("NUL") Description On-board Defaults 0x6F ("o") 0x00 0x72 ("r") 0x00 0x61 ("a") 0x00 0x67 ("g") 0x00 0x65 ("e") 0x00 0x20 (" ") 0x00 0x41 ("A") 0x00 0x64 ("d") 0x00 0x61 ("a") 0x00 0x70 ("p") 0x00 0x74 ("t") 0x00 0x65 ("e") 0x00 0x72 ("r") 0x00 0x00 Table 10 - String Descriptors Descriptor Requirements Descriptors programmed into an I2C memory device must observe the following constraints. String Descriptor Indexes An index of 0x00 indicates the string is absent. If the string descriptor is present, the index value is the beginning address location divided by 2. String descriptors must not cross I2C memory device block boundaries, i.e., the starting address must be moved to the next I2C memory device boundary. Pipes The ISD-300A1 provides four USB pipes: Default Control, Bulk Out, Bulk In, and Interrupt. Default Control Pipe The default pipe is used to transport standard, class and vendor-specific USB requests to the ISD-300A1. Bulk Out Pipe 21 October 19, 2001 ISD-300A1 The Bulk Out pipe is used to send commands and data to an attached mass storage device. Maximum packet size is 64 bytes in FS operation, 512 bytes in HS operation. Bulk In Pipe The Bulk In pipe is used to receive status and read data from an attached mass storage device. Maximum packet size is 64 bytes in FS operation, 512 bytes in HS operation. Interrupt Pipe The Interrupt pipe implemented in the ISD-300A1 serves two purposes: 1) Some legacy software applications require the endpoint to exist for correct operation, and 2) to enable systems to request service by the host. For more information, see the SYS_IRQ Pin section on page 41 of this document. Requests The ISD-300A1 responds to three different types of request: * Standard USB device requests * Mass Storage Class Bulk-Only requests * Vendor-specific requests Standard Requests The ISD-300A1 supports all USB standard device requests except the optional Set Descriptor request. These requests, which are described in Chapter 9, Device Framework, of the USB Specification, are: * Clear Feature * Get Configuration * Get Descriptor (for information on String Descriptors, see String Descriptors on page 19) * Get Interface * Get Status * Set Address * Set Configuration * Set Interface * Set Feature Mass Storage Class Bulk-Only Requests Mass Storage Class Bulk-Only requests supported by the ISD-300A1 are listed in Table 11. Label RESET GET_MAX_LUN bmRequestType 0x21 0xA1 bRequest 0xFF 0xFE wValue 0x0000 0x0000 wIndex Interface Interface wLength 0x0000 0x0001 Data [None] 1 byte Table 11 - Mass Storage Class Bulk-Only Requests RESET This request flushes all buffers and resets the pipes to their default states, resets all hardware registers to their default state, and basically causes the ISD-300A1 to enter a power-up reset state. Any STALL conditions or bulk data toggle bits remain unchanged. GET_MAX_LUN The ISD-300A1 returns one byte of data that contains the maximum LUNs supported by the device. This information is derived from the Last LUN Identifier configuration setting, bits (2:0) of configuration data located at address offset 0x8. For example, if the device supports four LUNs then the LUNs would be 22 October 19, 2001 ISD-300A1 numbered from 0 to 3, and the Last LUN Identifier configuration data bit field should be set to 0x3. If no LUN is associated with the device, the Last LUN Identifier shall be set to 0x0. Vendor-Specific Requests Vendor specific requests supported by the ISD-300A1 are listed in Table 12. The ISD-300A1 will STALL any vendor specific request if not configured by the USB host (USB configuration is 0). Label LOAD_CONFIG_DATA READ_CONFIG_DATA SOFT_RESET CMD_QUEUING_CONTROL BOGUS_READ LOAD_MFG_DATA bmRequestType 0x40 0xC0 0x40 0x40 0xC0 0x40 bRequest 0x01 0x02 0x03 0x04 0x01 0x05 wValue Data Source Data Source 0x0000 Queuing Control 0xXXXX Disable / Enable 0x0000 WIndex Starting Address Starting Address 0x0000 0x0000 0xXXXX 0x0000 (starting address) 0x0000 WLength Data Length Data Length 0x0000 0x0000 0xXXXX Data Length Data Length Data Configuration Data Configuration Data [None] [None] Null byte data Mfg. test data READ_MFG_DATA 0xC0 0x06 Mfg. test data Table 12 - Vendor-Specific Requests LOAD_CONFIG_DATA This request enables configuration data writes to the data source specified by the wValue field. The wIndex field specifies the starting address and the wLength field denotes the data length in bytes. Legal values for wValue are as follows: 0x0000 0x0002 Configuration bytes, address range 0x2 - 0xF External I2C memory device Configuration byte writes must be constrained to addresses 0x2 through 0xF, as shown in Table 4 - ISD300A1 Configuration Bytes on page 14. Attempts to write outside this address space will result in a STALL condition. Configuration byte writes only overwrite ISD-300A1 Configuration Byte registers, the original data source remains unchanged (I2C memory device, FBh identify data, or internal ROM). Writes to I2C memory devices shall only start on eight-byte boundaries, meaning that the address value must be evenly divisible by eight. Writes to I2C memory devices must not cross 256 byte page boundaries, i.e. start and finish write addresses must have equal modulo 256 values. Write operations with beginning and end addresses that do not fall in the same 256 byte page will result in a STALL condition. Illegal values for wValue as well as attempts to write to an I2C memory device when none is connected will result in a STALL condition. READ_CONFIG_DATA This USB request allows data retrieval from the data source specified by the wValue field. Data is retrieved beginning at the address specified by the wIndex field. The wLength field denotes the length in bytes of data requested from the data source. Legal values for wValue are as follows: 23 October 19, 2001 ISD-300A1 0x0000 0x0001 0x0002 0x0003 Configuration bytes, addresses 0x0 - 0xF only Internal ROM External I2C memory device Vendor-specific identify (FBh) data Illegal values for wValue will result in a STALL condition on the USB port. Attempted reads from an I2C memory device when none is connected or attempted reads from FBh data when not in I_MODE will result in a STALL condition. Attempts to read configuration bytes with starting addresses greater than 0xF will also result in a STALL condition. SOFT_RESET This request resets the ISD-300A1's data path control state machines, buffer RAM and command queue. The attached device is not reset. This USB request is required for error recovery while complex command queuing is enabled. Issuing a SOFT_RESET when complex command queuing is not enabled will result in a STALL condition. CMD_QUEUING_CONTROL This request sets the type of command queuing used by the ISD-300A1. Command queuing is a vendor specific feature of the ISD-300A1 that allows the CBW (refer to the USB Mass Storage Class Bulk Only Transport Specification) and possibly data for a new command to be transferred before the CSW for the previous command has been sent. Queuing commands can hide delays between the CBW, data, and CSW of a command and between commands, and thus improve overall system performance. The ISD-300A1 supports two types of command queuing: simple and complex. Simple Command Queuing In simple command queuing the ISD-300A1 stops when there is a phase error and does not process a queued CBW. But when there is a device error the ISD-300A1 continues and processes the queued command. It is up to the host to notice the "command failed" status in the CSW for the first command and recover from the error even though the subsequent queued command might have changed the state of the attached device after the error occurred. 24 October 19, 2001 ISD-300A1 Complex Command Queuing In complex command queuing the ISD-300A1 stops processing commands in the event of a device error just as it does for a phase error. This preserves the state of the attached device. The SOFT_RESET command is available when complex command queuing is enabled to allow the host to reset the ISD300A1 and discard any queued commands or data without resetting the attached device. After the SOFT_RESET the host can send another CBW to query the device for more information about the error or re-issue the failed command. Legal values for wValue are as follows: 0x0000 0x0001 Simple Command Queuing (Power-on reset default) Complex Command Queuing BOGUS_READ This USB request is present for legacy software reasons - some USB drivers require this command to exist for proper operation. The ISD-300A1 will return the requested amount of zero filled data packets. LOAD_MFG_DATA This USB request is used to enable and control Manufacturing Test Mode operation. Manufacturing Test Mode is provided as a means to implement board/system level interconnect tests. During Manufacturing Test Mode operation, all outputs not associated directly with USB operation are controllable. Normal state machine and register control of output pins are disabled. Control of the select ISD-300A1 IO pins and their 3-state controls are mapped to the USB data packet associated with this request. (See Table 13 - LOAD_MFG_DATA Data Block Bit Map for explanation of the required LOAD_MFG_DATA data packet format.) The wValue field enables/disables Manufacturing Test Mode operation. All Manufacturing Test Mode operation requests must contain a complete data packet (wLength field set to 0x0007) and start from the beginning of the register chain (wIndex field set to 0x0000). Legal values for wValue are as follows: 0x0000 0x0001 Normal operation mode - writing this wValue returns the ISD-300A1 to normal operation regardless of previous command data sets (power-on reset default). Manufacturing Test Mode - manufacturing test registers control specific outputs cells of the ISD-300A1 to enable board level testing in the manufacturing environment. Legal values for wLength are as follows: 0x0000 Valid only when wValue = 0x0000; when disabling Manufacturing Test Mode of operation. 0x0007 Valid only when wValue = 0x0001. For proper Manufacturing Test Mode operation, wLength must equal 0x0007. Any data packet lengths greater than 7 will result in a STALL condition. 25 October 19, 2001 ISD-300A1 Table 13 shows the bit-wise test control register mapping of the data packet associated with the LOAD_MFG_DATA vendor specific USB command. Byte 0 0 0 0 0 0 0 1 1 1 1 1 2 3 4 5 5 6 6 Bit(s) 1:0 2 3 4 5 6 7 0 2:1 5:3 6 7 7:0 7:0 7:0 1:0 7:2 3:0 7:4 Test / 3-State Control Register Name NLED[1:0] NPWR500 NATA_RESET NDIOW NDIOR NDMACK ATA_PU_EN ATA_PD_EN NCS[1:0] DA[2:0] NLOWPWR DD[15:0] 3-State Active hi 3-state buffer enable for ATA data bus. DD[7:0] DD[15:8] GPIO[7:0] GPIO[9:8] GPIO[5:0] 3-State Enable Active hi 3-state buffer enable for each GPIO pin GPIO[9:6] 3-State Enable Active hi 3-state buffer enable for each GPIO pin Reserved, software must write 0000b Table 13 - LOAD_MFG_DATA Data Block Bit Map 26 October 19, 2001 ISD-300A1 READ_MFG_DATA This USB request returns a "snapshot in time" of select ISD-300A1 input pins. The input pin states are bitwise mapped to the USB data packed associated with this request. ISD-300A1 input pins not associated directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode operation. This request is independent of normal ISD-300A1 state machine control or Manufacturing Test Mode write operations. See Table 14 - READ_MFG_DATA Data Block Bit Map for an explanation of the READ_MFG_DATA data packet format. Legal values for wValue are as follows: 0x0000 wValue must be set to 0x0000. Legal values for wLength are as follows: 0x0001 - 0x0008 Any data packet lengths greater than 0x0008 will result in a STALL condition. Table 14 shows the bit-wise input pin mapping of the data packet associated with the READ_MFG_DATA vendor specific USB command. All input and bi-directional pin values are taken from the pin. Byte 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 3 4 5 6 6 6 7 7 7 7 Bit(s) 0 1 2 3 3 5 6 7 0 1 3:2 4 5 6 7 0 1 2 4:3 7:5 7:0 7:0 7:0 1:0 2 7:3 4:0 5 6 7 Pin Name DRV_PWR_VALID VBUS_PWR_VALID VBUS_POWERED DISK_READY SYS_IRQ IORDY DMARQ I_MODE NCART_DET N_EJECT NLED[1:0] NPRW500 (output register value only) NATA_RESET (output register value only) NDIOW (output register value only) NDIOR (output register value only) NDMACK (output register value only) ATA_PU_EN (output register value only) ATA_PD_EN (output register value only) NCS[1:0] (output register value only) DA[2:0] (output register value only) DD[7:0] DD[15:8] GPIO[7:0] GPIO[9:8] DD[15:0] 3-State Control (internal register) GPIO[4:0] 3-State Control (internal register) GPIO[9:5] 3-State Control (internal register) MFG_SEL (manufacturing test mode enable) NLOWPWR (output register value only) ATA_EN Table 14 - READ_MFG_DATA Data Block Bit Map 27 October 19, 2001 ISD-300A1 ATA/ATAPI Interface The ATA/ATAPI port on the ISD-300A1 is compliant with the Information Technology - AT Attachment with Packet Interface - 5 (ATA/ATAPI-5) Specification, T13/1321D Rev 3. The ISD-300A1 supports both ATAPI packet commands as well as ATA commands (by use of ATA Command Blocks). Additionally, the ISD-300A1 translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class BOT drivers. The ISD-300A1 also provides a vendorspecific "event notify" ATA command to automatically communicate certain USB and system events to the attached device. Protocol The ISD-300A1 supports command protocol flows as defined in the ATA/ATAPI-5 Specification. Commands are grouped into different classes, based on the protocol followed for command execution. The ATA/ATAPI interface supports the following clarifications: * * * * Immediately after the reset recovery period, the ISD-300A1 will write 0x00 to the Device Control register. Arbitrary byte count transfers are supported. 16-bit data reads and writes are supported. 8-bit data transfers are not supported. Reset Mapping The ATA/ATAPI interface responds to several resets: Power-on, USB, MSC, and Vendor-specific Soft reset. In the case of a power-on reset, a full device initialization is performed. FBh data is retrieved and stored if the I_MODE pin is set active. In the cases of USB reset and MSC reset, a partial initialization is performed which excludes all attempts to perform Identify Device commands. In the case of a Vendor-specific Soft reset, only the internal ISD-300A1 state machines are reset. Device Requirements Attached mass storage devices must support the following: ATA Reset, A1h, FBh After deassertion of ATA_NRESET, BSY and DRQ must be cleared by the device within the ATA Initialization Timeout configuration setting value. ATA Polling Device The device shall be capable of being a polling only device. The ATA signal INTRQ is not used by the ISD-300A1. 28 October 19, 2001 ISD-300A1 ATA Initialization Timeout ISD-300A1 internal ROM has a default configuration value of 8.2 seconds for ATA Initialization Timeout. When I_MODE operation is utilized, the default ATA Initialization Timeout value is used to retrieve FBh data. Once the vendor specific Identify (FBh) command completes, the default value is overridden with the FBh data value. If an I2C memory device is utilized for ISD-300A1 configuration and USB descriptor data, the ATA Initialization Timeout value is loaded from the I2C memory device prior to any ATA interface activity. Reset Recovery is 3 ms. Figure 2 graphically defines "Initialization Timeout" and "Reset Recovery". reset assertion initialization timeout ATA_NRESET reset recovery nDIOR/nDIOW Figure 2 - ATA Reset Protocol 29 October 19, 2001 ISD-300A1 ATA Command Block ATA commands for the ISD-300A1 are supported by command encoding in the command block portion of the MSC Command Block Wrapper (CBW). Refer to the USB Mass Storage Class (MSC) Bulk Only Transport Specification for information on CBW formatting. The ATA Command Block (ATACB) provides a means of passing ATA commands and ATA register accesses for execution. The ATACB resides in the CBWCB portion of the CBW. The ATACB is distinguished from other command blocks by the first two bytes of the command block matching the wATACBSignature. Only command blocks that have a valid wATACBSignature are interpreted as ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB shall remain as defined in the USB Mass Storage Class Bulk Only Transport Specification. The ATACB shall be 16 bytes in length. The following table and text defines the fields of the ATACB. Byte 0-1 2 3 4 5-12 13-15 Table 15 - ATA Command Block Formatting Field Descriptions wATACBSignature - This signature indicates that the CBWCB contains an ATACB. The signature field shall contain the ATA Command Designator value obtained from ISD-300A1 configuration space to indicate an ATACB (the default value is 0x2424). Devices capable of accepting only ATA Command Blocks shall return a command failed status if the wATACBSignature is not correct. bmATACBActionSelect - The bit fields of this register shall control the execution of the ATACB. Refer to Figure 3- ATA Command Block Flow Diagram for further clarification. The bitmap of the bmATACBActionSelect shall be defined as follows: IdentifyPacketDevice - ATA/ATAPI Identify Packet Device Command. Setting Bit 7 IdentifyPacketDevice indicates the data phase will contain ATAPI (A1h) or ATA (Ech) IDENTIFY device data. Setting IdentifyPacketDevice when the data phase is not IDENTIFY data will cause undetermined device behavior. 0 = Normal operation. 1 = Data phase of command will contain ATAPI or ATA IDENTIFY data, allowing the device to parse data for required device information. Bit 6 UDMACommand - Ultra DMA Data Transfer Enable (Multi-word DMA not supported). Setting UDMA Command with non-UDMA capable devices or using it with non-UDMA commands will cause undetermined behavior. 0 = Do not use DMA data transfers (PIO transfers only). 1 = Utilize Ultra DMA for data transfers (device must be capable). 30 7 6 5 4 3 2 1 0 wATACBSignature bmATACBActionSelect bmATACBRegisterSelect bATACBTransferBlockCount bATACBTaskFileWriteData Reserved (0) October 19, 2001 ISD-300A1 Bit 5 Bits 4-3 Bit 2 Bit 1 Bit 0 DEVOverride - Use the DEV value specified in the ATACB. 0 = The DEV bit value will be determined from ISD-300A1 Configuration data (0x5 bit 5). 1= The DEV bit value will be determined from the ATACB(0xB bit 4). DPErrorOverride(1:0) - Device and Phase Error Override. These bits shall not be set in conjunction with bmATACBActionSelect TaskFileRead. The order of precedence for error override shall be dependant on the amount of data left to transfer when the error is detected, as depicted in the ATACB Command Flow diagram. 00 = Data accesses are halted if a device or phase error is detected. 01 = Phase error conditions are not used to qualify the occurrence of data accesses. 10 = Device error conditions are not used to qualify the occurrence of data accesses. 11 = Neither device error or phase error conditions are used to qualify the occurrence of data accesses. PollAltStatOverride - Poll ALTSTAT Override. 0 = The Alternate Status registered shall be polled until BSY=0 before proceeding with the ATACB operation. 1 = Execution of the ATACB shall proceed with the data transfer without polling the Alternate Status register until BSY=0. DeviceSelectionOverride - Device Selection Override. This bit shall not be set in conjunction with bmATACBActionSelect TaskFileRead. 0 = Device selection shall be performed prior to command register write accesses. 1 = Device selection shall not be performed prior to command register write accesses. TaskFileRead - Read and return the task file register data selected in bmATACBRegisterSelect. If TaskFileRead is set, the dCBWDataTransferLength field must be set to 8. 0 = Execute ATACB command and data transfer (if any). 1 = Only task file registers selected in bmATACBRegisterSelect shall be read. Task file registers not selected in bmATACBRegisterSelect shall not be accessed and 00h shall be returned for the unselected register data. bmATACBRegisterSelect - Setting the appropriate bit fields shall cause the taskfile read or write register access to occur. Taskfile read data shall always be 8 bytes in length. Unselected taskfile register data shall be returned as 00h. Taskfile register accesses shall occur in sequential order as shown (Bit 0 first, Bit 7 last). The bmATACBRegisterSelect bitmap shall be as defined below. Bit 0 (3F6h) Device Control / Alternate Status Bit 1 (1F1h) Features / Error Bit 2 (1F2h) Sector Count Bit 3 (1F3h) Sector Number Bit 4 (1F4h) Cylinder Low Bit 5 (1F5h) Cylinder High Bit 6 (1F6h) Device / Head Bit 7 (1F7h) Command / Status bATACBTransferBlockCount - This value shall denote the maximum requested block size in 512 byte blocks. This variable shall be set to the value last used for "Sectors per block" in the SET_MULTIPLE_MODE command. Valid values are 0, 1, 2, 4, 8, 16, 32, 64, and 128 (0 indicates 256 sectors per block). Command failed status shall be returned if an invalid value is detected in the ATACB. Non-multiple commands shall set this value to 1 (block size of 512 bytes). 31 October 19, 2001 ISD-300A1 bATACBTaskFileWriteData - ATA register data used on ATA command or PIO write operations. Only data entries that have the associated bmATACBRegisterSelect bit set shall be required to have valid data. ATACB Address offset 5h (3F6h) Device Control ATACB Address offset 6h (1F1h) Features ATACB Address offset 7h (1F2h) Sector Count ATACB Address offset 8h (1F3h) Sector Number ATACB Address offset 9h (1F4h) Cylinder Low ATACB Address offset Ah (1F5h) Cylinder High ATACB Address offset Bh (1F6h) Device ATACB Address offset Ch (1F7h) Command 32 October 19, 2001 ISD-300A1 ATA Command Flow Figure 3 shows the flow of ATA commands, specifically the actions taken by the ISD-300A1 based upon how the ATA Command Block is configured. page 1 of 2 Command Fail OR other command block specification assumed no wATACB Signature detected yes Latch bmATACBActionSelect set ATACB PollAltStat Override Latch bmATACBRegisterSelect clear Poll ATA Alternate Status until BSY=0 and store ERR and DRQ bits. set ATACB TaskFileRead clear Set TransferLength = dCBWDataTransferLength Read registers selected in bmATACBRegisterSelect. Latch TransferBlockSize ATACB DeviceSelection Override set DONE clear Perform ATA Device Selection. The device shall specify the value for the DEV bit. Write ATA registers selected in bmATACBRegisterSelect with the bATACBTaskFileWriteData Note: Only ATA registers selected in bmATACBRegisterSelect are read. ATA registers not read are zero filled in the 8 bytes of returned data. dCBWDataTransferLength must be set to 8. C set Note: If no ATA registers are selected then no ATA registers are written. The device shall specify the value for the DEV bit when writing the DEVICE_HEAD register unless the ATACB DEVOverride bit is set.. ATACB PollAltStat Override clear Poll ATA Alternate Status until BSY=0 and store ERR and DRQ bits. B A 33 October 19, 2001 ISD-300A1 page 2 of 2 A Note: DRQ and ERR bit information come from last read of ATA Alternate Status register. set yes TransferLength > 0 no ATACB DPErrorOverride (0) ATACB DPErrorOverride (0) set clear set clear clear DRQ clear DRQ set Phase Error clear ATACB DPErrorOverride (1) set clear ERR set set ERR clear Read ATA Status to clear INTRQ and ignore results Read ATA Status to clear INTRQ and ignore results B Fail Read ATA Status to clear INTRQ and ignore results yes TransferLength > 0 no TransferLength < BlockSize*512? yes Set ByteCount = DataTransferLength Set TransferLength = 0 no Read ERR Register Set ByteCount = (BlockSize*512) Set TransferLength = TransferLength (BlockSize*512) Done Transfer ByteCount bytes specified by Direction in bmCBWFlags. C Figure 3- ATA Command Block Flow Diagram 34 October 19, 2001 ISD-300A1 Vendor-Specific ATA Commands There are two vendor-specific ATA commands implemented in the ISD-300A1. These commands are shown in Table 16. Label IDENTIFY EVENT_NOTIFY Command Code FBh Specified in Configuration Data Description This command is used to read ISD-300A1 configuration data and USB descriptor data from an attached mass storage device. This command communicates certain events to the device and is executed as the events occur. Table 16 - Vendor-Specific ATA Commands IDENTIFY The vendor-specific Identify (FBh) command enables the ISD-300A1 to request configuration and USB descriptor information from an attached mass storage device. Command Code FBh Protocol PIO data-in (refer to ATA/ATAPI-5 Specification, section 9.7). Identification Register Writes Register Features Sector Count Sector Number Cylinder Low Cylinder High Device/Head Command 7 6 5 4 N/A N/A N/A N/A N/A obs N/A obs DEV FBh 0 0 0 1 3 2 1 0 Table 17 - Identification Register Writes Device/Head register - The DEV bit indicates the selected device. Identification Register Reads Register Error Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status 7 6 5 4 N/A N/A N/A N/A N/A obs BSY N/A N/A obs N/A DEV N/A N/A DRQ N/A N/A N/A N/A N/A ERR 3 2 1 0 Table 18 - Identification Register Reads 35 October 19, 2001 ISD-300A1 Device/Head register - The DEV bit indicates the selected device. Status register - BSY shall be cleared to zero upon command completion. DRDY shall be set to one. DF (Device Fault) shall be cleared to zero. DRQ shall be cleared to zero. ERR shall be cleared to zero. Device Error Indication If the device does not support this command, the device shall return command aborted. Otherwise, the device shall not report an error. Description When the command is issued, the device sets the BSY bit to one, and prepares to transfer 512 bytes of configuration/descriptor data to the ISD-300A1. Note: Configuration and descriptor information is limited to 256 bytes in length. Data beyond 256 bytes (bytes 256-511) is read by the ISD-300A1 but ignored. The device then sets DRQ to one and clears BSY to zero. The arrangement and meaning of the FBh data bytes are specified in Table 3, Table 7, Table 8, Table 9, Table 10, and Table 11. An example of FBh programming is shown in Appendix A. EVENT_NOTIFY The vendor-specific Event-notify command enables the ISD-300A1 to communicate the occurrence of certain USB and system events to the attached device. Command Code Specified in the ISD-300A1 Configuration Bytes, address 0x2. Programming the command code to 0x00 disables the event-notify feature. Protocol Non-data (refer to ATA/ATAPI-5 Specification, section 9.9). Notification Register Writes Register Features 7 USB Reset Reserved 6 Class Specific Reset Reserved 5 USB Suspend Reserved 4 USB Resume Reserved 3 Cartridge Insert Reserved 2 Cartridge Release Reserved 1 Eject Button Press USB High Speed 0 Eject Button Release USB Full Speed Sector Count Sector Number Cylinder Low Cylinder High Device/Head Command N/A STATE0 STATE1 N/A Specified in the ISD-300A1 Configuration Bytes Table 19 - Event Notify ATA Command Features register - The USB Reset bit indicates that a USB Reset event has occurred. The Class Specific Reset bit indicates that an MSC Reset was issued by the host. The USB Suspend bit indicates that the USB bus has gone into suspend. 36 October 19, 2001 ISD-300A1 The USB Resume bit denotes that the USB bus is no longer in suspend. The Cartridge Insert bit is set when the device media is inserted. The Cartridge Release bit is set when the device media is ejected. The Eject Button Press bit is set when the eject button on the device is pressed. The Eject Button Release bit is set when the eject button on the device is released. Sector Count - The USB Full Speed bit indicates the USB bus is now operating in full speed mode (12 Mbit). The USB High Speed bit indicates the USB bus is now operating in high speed mode (480 Mbit). Cylinder Low - STATE0 STATE0 is written with the value of NSTATE0 obtained from the previously completed event notification command. Assertion of NRESET resets STATE0 to 0x00. Cylinder High - STATE1 STATE1 is written with the value of NSTATE1 obtained from the previously completed event notification command. Assertion of NRESET resets STATE1 to 0x00. Notification Register Reads Register Error Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status 7 6 5 4 3 2 1 0 BSY N/A N/A N/A N/A N/A NSTATE0 NSTATE1 N/A N/A DRQ N/A N/A N/A Table 20 - Event Notify Drive Status Cylinder Low - NSTATE0 NSTATE0 is read from the device and stored for use as STATE0 during the next execution of the event notification command. NSTATE0 provides temporary non-volatile storage for devices whose power is controlled by NPWR500 (typically VBUS powered systems). This allows the device to store information prior to entering a USB suspend state for retrieval after resuming from the USB low power state. Cylinder High - NSTATE1 NSTATE1 is read from the device and stored for use as STATE0 during the next execution of the event notification command. NSTATE0 provides temporary non-volatile storage for devices whose power is controlled by NPWR500 (typically VBUS powered systems). This allows the device to store information prior to entering a USB suspend state for retrieval after resuming from the USB low power state. Note that a USB reset from the host may interrupt the collection of data. The device must accommodate the potential for this occurrence. Status register - BSY shall be cleared to zero upon command completion. DRQ shall be cleared to zero. 37 October 19, 2001 ISD-300A1 Error Outputs If the device does not support this command, the device shall return command aborted. Otherwise, the device shall not report an error. Description When the event notification command is issued, the ISD-300A1 waits until the device clears BSY and DRQ to zero before beginning register writes. After writing the input registers, the ISD-300A1 waits for BSY and DRQ cleared to zero and then reads the next state information (NSTATE). The event notification command is issued following every reset of the device and following the power-on reset device initialization sequence. The event notification command is also issued after any of the events reported in the event notification data take place. If any combination of mating events (mating events are defined as USB HS/FS, suspend/resume, cartridge insert/release, eject press/release, and USB/class reset) take place before the ISD-300A1 can issue the event notification command to the device, the following will occur: 1. 2. Send an event notification command showing all events. Send a subsequent event notification command showing only the most recent of any mated events. If an event notification command does not complete for any reason (such as an incoming reset), the ISD300A1 will re-issue the command (with any new event data) until it completes successfully. Success of the command does NOT depend upon the ERR bit. If the DRQ bit is set in response to an event notification, the ISD-300A1 will continue to poll (this debug feature makes device incompatibility obvious). Power Management The ISD-300A1 is capable of offering two types of system power configurations. * Self-Powered - VBUS current is limited to 100 mA or less. * Bus-Powered - VBUS current is limited to 500 mA or less. The ISD-300A1 dynamically operates in a self or bus powered system depending upon the state of the VBUS_POWERED input. Control Pins VBUS_POWERED Pin The VBUS_POWERED input pin indicates the amount of system current drawn from VBUS. The VBUS powered input is used to qualify: * The response for a GET_STATUS USB request. * An ISD-300A1 asynchronous reset in the following cases: o If VBUS_POWERED is asserted high and the host has set the USB configuration for self powered operation. o If VBUS_POWERED is detected changing state when USB configuration is set to 0. * Which USB descriptors are presented to the host. If asserted, the first descriptor set is returned. If de-asserted, the second descriptor set is returned. Setting VBUS_POWERED inactive dictates the system is self powered, drawing up to the value of current returned in the bMaxPower field (100 mA maximum) or less from VBUS. Setting VBUS_POWERED active indicates the system is capable of drawing up to the amount present in the bMaxPower USB descriptor field (500 mA maximum). 38 October 19, 2001 ISD-300A1 DRV_PWR_VALID Pin The DRV_PWR_VALID input pin is typically enabled only in Hybrid powered systems, or systems in which the ISD-300A1 receives power from VBUS, and the device receives power from another source. In VBUS or self powered systems DRV_PWR_VALID is typically not utilized. In Hybrid powered systems, DRV_PWR_VALID indicates if the device is powered or at least attached and qualifies device operation. DRV_PWR_VALID active polarity and enabling is controlled during ISD-300A1 configuration. It is active high in systems that can supply a power indication from the drive. It is active low in systems that utilize a "grounding scheme" to indicate when the cable is connected to the device. If enabled, and DRV_PWR_VALID is not determined active after the ISD-300A1 configuration data is loaded, the ISD300A1 enters a low power mode of operation (similar to USB suspend state when in VBUS powered operation. See Table 21 - ATA Interface Line States on page 40 for more information). Asserting DRV_PWR_VALID enables resume from the low power operation state. This signal may also be used in conjunction with ATA_EN to force the ISD-300A1 to disable the USB interface and operate in a low power state when sharing the ATA interface. VBUS_PWR_VALID Pin This input pin indicates that VBUS power is present at the USB connector. VBUS_PWR_VALID qualifies driving the system's 1.5K ohm pull-up resistor on D+ when the system is externally powered (the USB specification only allows the device to source power to D+ when the host is powered). After the ISD300A1 configuration data is loaded, if VBUS_PWR_VALID is inactive the ISD-300A1 enters a low power mode of operation. Asserting VBUS_PWR_VALID resumes operation from the low power state. DISK_READY Pin This input pin indicates the attached device is powered and ready to begin communication with the ISD300A1. DISK_READY qualifies the start of the ISD-300A1's initialization sequence. A state change from 0 to 1 on DISK_READY will cause the ISD-300A1 to wait for 25 ms before asserting NATA_RESET and re-initialize the device. The ATA interface state machines remain inactive and all of the ATA interface signals are driven logic `0' if DISK_READY is not asserted (assuming ATA_EN = `1'). This input is not used in conjunction with DRV_PWR_VALID, and should be tied to logic `1' in hybrid powered systems. DISK_READY is filtered for 25 ms on the rising edge and cleared asynchronously on the falling edge. NLOWPWR Pin When active, the NLOWPWR pin indicates the ISD-300A1 is operating in a low power state. NPWR500 Pin The NPWR500 output pin indicates the USB host has configured the ISD-300A1 USB interface for VBUS powered operation (VBUS_POWERED pin active), granting the requested amount of power for the peripheral (the bMaxPower entry from descriptor set 1). In the case of a USB suspend condition, NPWR500 is de-asserted and the ISD-300A1 enters a low power state of operation. Upon a resume condition, the ISD-300A1 will resume normal operation and restore NPWR500 accordingly. Note: ISD300A1 power sources should not be controlled at any time by using the NPWR500 pin. 39 October 19, 2001 ISD-300A1 ATA Interface Line States The following table depicts the ATA interface line state dependency with the various controlling input pins. Control Signals VBUS_SUSPEND OPERATIONAL ATA Interface / Power Management DD[15:0], NCS[1:0], DA[2:0], ATA_PD_EN, ATA_PU_EN, NDIOR, NDIOW, NDMACK, NATA_RESET = '0' ATA_PD_EN = `0' ATA_PU_EN = `1' ( NCS[1:0], DA[2:0] NDIOR, NDIOW, NDMACK, NATA_RESET = `1' when the ATA interface is idle) ATA_PD_EN, ATA_PU_EN, and all other ATA interface signals = `Z' ATA_HIZ NRESET ATA_EN DRV_PWR_VALID (1) DISK_READY 0 X 1 1 1 Notes: 1 0 1 1 1 X X 0 1 1 X X X (= 1) 0 1 VBUS_SUSPEND state for the ATA interface. ATA_HIZ. All ATA interface signals are 3-stated (hi-Z). VBUS_SUSPEND state for ATA interface. This is a Hybrid powered application (VBUS powered ISD-300A1, brick powered ATA/ATAPI device) VBUS_SUSPEND state for the ATA interface. OPERATIONAL. VBUS / Brick powered normal operation mode (1) DRV_PWR_VALID is active (polarity is correct) OR is disabled by configuration data. Table 21 - ATA Interface Line States 40 October 19, 2001 ISD-300A1 Operation Control NEJECT, NCART_DET Pins - USB Remote Wakeup and Event Notification These pins are used to trigger USB remote-wakeup as well as ATA Event Notification. When asserted low NEJECT indicates that a media eject request occurred. When asserted low NCART_DET indicates that a media cartridge is present. For NEJECT, the pin value must remain static for 10 ms before any state change is detected by internal state machine logic. For NCART_DET, any asynchronous change in state after the signal retains a static value for more than 10 ms is detected by internal state machine logic. GPIO Pins - General Purpose IO The GPIO pins enable general purpose IO for miscellaneous use. Each GPIO pin has independent 3-state control, with an internal pull down resistor (50K ohm typically). The GPIO pins input, output, and 3-state control span three bytes of configuration space. The chosen implementation methodology does not allow read and write operations between GPIO[9:8] and GPIO[7:0] to occur during the same clock period. ! During read operations GPIO[9:8] are sampled one clock period (33ns) prior to GPIO[7:0] (assuming the read operation spans all GPIO register space). ! During write operations GPIO[9:8] 3-state control and output values are latched one clock period (33ns) prior to GPIO[7:0] 3-state control and output values (assuming the write operation spans all GPIO register space). I_MODE Pin - Vendor Specific Identify (FBh) ATA Command (I_MODE) Asserting the I_MODE pin high enables ISD-300A1 configuration and USB Descriptor data retrieval from an attached device via a vendor specific ATA command (FBh) rather than an external I2C memory device. Unlike operation with an external I2C memory device, I_MODE operation requires the attached device first be initialized and FBh data retrieved before the ISD-300A1 can allow USB enumeration. To meet USB specification requirements, I_MODE operation must be limited to systems that draw 100 mA or less from VBUS prior to USB enumeration. SYS_IRQ Pin - USB Interrupt The SYS_IRQ pin provides a way for systems to request service from host software by use of the USB Interrupt pipe. If the ISD-300A1 has no pending interrupt data to return, USB interrupt pipe data requests are NAK'd. If pending data is available, the ISD-300A1 returns 16-bits of data indicating the state of the GPIO[9:0] and DISK_READY pins. Table 22 and Figure 4 depicts the bit map and latching algorithm incorporated by the ISD-300A1. USB Interrupt Data Byte 1 Bit Map 6 5 4 3 2 1 0 0 0 0 DISK_READY GPIO[9] 7 0 0 GPIO[8] 7 GPIO[7] USB Interrupt Data Byte 0 Bit Map 6 5 4 3 2 1 GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] 0 GPIO[0] Table 22 - USB Interrupt Pipe Data 41 October 19, 2001 ISD-300A1 No No USB Interrupt Pipe Polled? SYS_IRQ=1? Yes Yes Int_Data = 1? No Yes Latch State of IO Pins Set Int_Data = 1 No NAK Request Yes Int_Data = 0 and SYS_IRQ=0? Return Interrupt Data Set Int_Data = 0 Figure 4 - SYS_IRQ - USB Interrupt Pipe ATA_EN Pin - ATA Interface Disabled The ATA_EN pin allows ATA bus sharing with other host devices. Asserting ATA_EN low causes the ISD-300A1 to 3-state all ATA bus interface pins hi-Z and suspend ATA state machine activity, otherwise leaving the ISD-300A1 operational (USB operation continues). Asserting ATA_EN high resumes normal operation. To disable USB operation and the ATA interface, the DRIVE_PWR_VALID signal can be used in conjunction with ATA_EN to force the ISD-300A1 into a low power state until normal operation is resumed. ATA_PU_EN Pin - ATA Interface Pull-up Resistor Source This output provides control for the required host pull-up resistors on the ATA interface. ATA_PU_EN is 3-stated hi-Z when ATA_EN is low. ATA_PD_EN Pin - ATA Interface Pull-down Resistor Sink This output provides control for the required host pull-down resistors on the ATA interface. ATA_PD_EN is 3-stated hi-Z when ATA_EN is low. 42 October 19, 2001 ISD-300A1 TEST<3:0> Pins - Test Modes TEST(3:0) 0000 0001 0010 0011 0100 0101 Mode Description Normal Mode - This is the default mode of operation, or run time mode. Pull-downs are on. Normal Mode XCVR Muxout - debug mode 1. See XCVR Mux-out Mode below. Limbo - Setting this mode disables most outputs. See Limbo Mode below. Input NandTree - Allows board level manufacturing tests. See Input NandTree Mode below. Bi-di NandTree - Allows board level manufacturing tests. See Bi-di NandTree Mode below. SimTest - HDL simulation only test mode. Specific GPIO pins are multiplexed in this mode of operation: Short Timers GPIO[2] Short SRAM GPIO[1] Skip Identify GPIO[0] Scan Mode - Fab only test mode Reserved Normal Mode XCVR Mux-out - ASIC debug mode 2. See XCVR Mux-out Mode. Normal Mode XCVR Mux-out - ASIC debug mode 3. See XCVR Mux-out Mode. Normal Mode XCVR Mux-out - ASIC debug mode 4. See XCVR Mux-out Mode. Test Bus - SERDES Fab only test mode Test Bus - ROM Fab only test mode Test Bus - 256x8 SP SRAM. Fab only test mode Test Bus - 32x16 DP SRAM. Fab only test mode Test Bus - 4Kx16 DP SRAM. Fab only test mode 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 23 - Test Modes XCVR Mux-out Mode These modes of operation are similar to the Normal Mode of operation with various internal transceiver logic signals brought out through the GPIO and LED pins. These modes are intended only for Cypress ASIC qualification. The table below shows the mux-out scheme for each mode of operation. Pin # 38 39 40 42 44 45 46 47 48 49 94 95 ISD-300A1 Pin Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 NLED1 NLED0 Mode 1 - XCVR signal RXERROR RXBUSACT RXDOUT(0) RXDOUT(1) RXDOUT(2) RXDOUT(3) RXDOUT(4) RXDOUT(5) RXDOUT(6) RXDOUT(7) RXLSTBYT RXVALID Mode 2 - XCVR signal IHSDRVON CDRCLKEN CLK_30 CLK_60 LPBACK1 LPBACK0 LOCK IOST1 IOST0 HSRCVEN 0 PWRDOWN_XCVR 43 Mode 3 - XCVR signal TXREADY TXVALID TXDIN(0) TXDIN(1) TXDIN(2) TXDIN(3) TXDIN(4) TXDIN(5) TXDIN(6) TXDIN(7) RXACTIVE TXBUSACT Mode 4 - XCVR signal PUE CLRXVM CLRSVP CLRXISE0 CLRSDATA CNEN CLRCVEN CLTXOEN CLTXOSE0 CLTXDATA CONTJ CONTK October 19, 2001 ISD-300A1 Limbo Mode This mode of operation is provided to aid debug in manufacturing environments. The ISD-300A1 3-states (high Z) all output pins during Limbo mode operation with the exception of the XO pin. The XO pin output cell does not have 3-state control (always enabled), and thus must be disabled / disconnected by other means. Input NandTree Mode This mode tests the connectivity of all inputs and outputs. While in the Input NandTree Mode of operation, all bi-directional pins are wired as chain outputs. The results of the connectivity procedure will be seen on all bi-directional pins. The list below shows the connectivity order of the Input NandTree chain (beginning to end). Chain inputs: BUS_PWR_VALID, VBUS_POWERED, DRV_PWR_VALID, DISK_READY, SYS_IRQ, DMARQ, IORDY, NCART_DET, NEJECT, NRESET, I_MODE, ATA_EN Chain outputs: GPIO{9:0], DD[15:0], SDA Bi-di NandTree Mode This mode test the connectivity of all bi-directional inputs. While in the Bi-di NandTree Mode of operation, all bi-directional pins are wired as inputs and become part of the NandTree chain. The results of the connectivity procedure will be seen on all output only pins. The list below shows the connectivity order of the Bi-di NandTree chain (beginning to end). Chain inputs: GPIO[0:9], Note: GPIO[0] first, GPIO[9] last DD[15], DD[0], DD[14], DD[1], DD[13], DD[2], DD[12], DD[3], DD[11], DD[4], DD[10], DD[5], DD[9], DD[6], DD[8], DD[7], Chain outputs: NLED[1:0], NPWR500, NATA_RESET, NDIOW, NDIOR, NDMACK, ATA_PU_EN, ATA_PD_EN, NCS[1:0], DA[2:0], NLOWPWR, SCL Pin connectivity in both NandTree modes can be tested with the following procedure: 1. 2. 3. 4. Set all inputs on the chain to `1'. Outputs will be `1'. Set first input to `0'. Outputs will toggle Set first input back to `1'. Outputs will toggle. Set '0' on the NandTree chain inputs from second input to the end of the chain (in order). The outputs will toggle with each input toggle, testing pad / IO cell connectivity. 44 October 19, 2001 ISD-300A1 Manufacturing Test Mode This mode of operation is provided for interconnect test in a manufacturing environment. During Manufacturing Test Mode operation, all outputs not associated directly with USB operation are controllable. Normal state machine and register control of output pins is disabled. ISD-300A1 input pins not associated directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode operation. Vendor specific USB commands are used to enable and control Manufacturing Test Mode operation and to sample input pin states. See Vendor-Specific Requests for more details on the LOAD_MFG_DATA and READ_MFG_DATA USB commands. External Circuitry USB, Crystal, and I2C Interface Connections 3.3V 3.3V ATA Interface RPU 1.5K 1.5 SDA SCL RREF 9.1 (1%) AVSS XI ISD-300A1 DP RSDP DM RSDM XO D36 Note: For High-speed operation, the 36 resistors on RSDM and RSDP combine with 9 internal impedance to provide 45 on D+ and D-, or 90 differential impedance. D+ 36 Analog GND Analog VCC Digital VCC Crystal Specifications: KDS AT-49, 10 pf load cap., 50 ppm. Crystals with different specifications than above will require modified circuit values for correct operation. 100 30MHz 9pF 9pF Figure 5 - External Components connection ATA Interface Considerations 1K Ohm Pull-down Resistor On DD<7> For "slave" devices, a 1K ohm pull-down resistor must be utilized on DD7 for ISD-300A1 based designs. This is required for proper operation of the ISD-300A1 master/slave device auto detection algorithm. If this modification is omitted, slave devices will take an excessive amount of time to initialize (around 30 seconds). In systems with only master devices this modification may be omitted. ATA_PD_EN and ATA_PU_EN Usage In Self Powered Systems These signals are controlled by ATA_EN, DRV_PWR_VALID, and DISK_READY. If these inputs are static, the ATA_Px_EN outputs can be left unconnected and the pull-up and pull-down resistors that normally connect to these outputs can be directly tied to the appropriate power rails. 45 October 19, 2001 ISD-300A1 ATA Interface Termination Design practices as outlined in the ATA/ATAPI-5 Specification for signal integrity should be followed with systems that utilize a ribbon cable interconnect between the ISD-300A1 ATA interface and the device, especially if Ultra Mode DMA is utilized. 3.3V Power Regulation In systems where the ATA/ATAPI device remains powered during ISD-300A1 low power operation (such as USB suspend state), the system design must insure the ISD-300A1 3.3V supply is not "back powered" through IO cell leakage current from the device's 5V ATA interface, raising the supply rail above safe operating limits. Typically this may be accomplished by utilizing a 1.5K ohm resistive current sink between the 3.3V supply and ground. VBUS Powered System Considerations GPIO Internal Pull Down Resistors All ISD-300A1 GPIO IO cells incorporate an internal pull down resistor (50K ohm typical). The system must insure the GPIO interface is at logic `0' to eliminate current draw during the USB suspend state. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Symbol VDD Vin Ta Tstrg Parameter 3.3 V IO Supply Input Pin Voltage Ambient Operating Temperature Range Storage Temperature Min -0.5 -0.5 -40 -65 Max 4.0 5.5 85 150 Units Volts Volts Celsius Celsius Table 24 - Absolute Maximum Ratings 46 October 19, 2001 ISD-300A1 Electrical Characteristics Voltage Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Power Supply Voltage Symbol VIL VIH VOL VOH VDD33 Test Conditions Min 2.0 2.4 3.0 Typ 3.3 3.3 Max 0.8 0.4 3.6 Unit V V V V V Note: (TA = 20 C, VDD33 = 3.3 V 10%, VSS = 0 V) Table 25 - Voltage Characteristics Operation Current Parameters - Typical High Speed VDD supply current (IDD) - Idle High Speed VDD supply current (IDD) - Active Full Speed VDD supply current (IDD) - Idle Full Speed VDD supply current (IDD) - Active Supply current w/ nRESET asserted Low power w/ USB remote wakeup enabled Low power w/o USB remote wakeup enabled Note: (TA = 20 C, VDD = 3.3 V 10%, VSS = 0 V) Table 26 - Power Supply Current Characteristics 180 mA (typ) < 200 mA (typ) 121 mA (typ) < 135 mA (typ) 90mA (typ) 2.7 mA (typ) < 20 A (typ) 47 October 19, 2001 ISD-300A1 Timing Characteristics I2C Memory Device Interface Timing The I2C memory device interface supports a subset of the I2C "slow mode" specification implementation document. Timing specifics are given below. Thigh Tlow SCL TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO SDA OUT TBUF TDSU SDA IN Figure 6 - I2C Memory Device Interface Timing I2C Parameter Clock high time Clock low time Start condition hold time Start condition setup time Data output hold time Data output setup time Stop condition setup time Required data valid before clock Min time bus must be free before next transmission Table 27 - I2C Memory Device Interface Timing Symbol Thigh Tlow THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TDSU TBUF Value 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 500 ns 5066 ns 48 October 19, 2001 ISD-300A1 SYS_IRQ Interface Timing The timing specifications for SYS_IRQ relative to the USB interrupt pipe data are given below. THD:IRQ SYS_IRQ TSU:DAT THD:DATA INPUT PIN Figure 7 - SYS_IRQ Interface Timing SYS_IRQ Parameter Interrupt pipe data set up time SYS_IRQ hold time Interrupt pipe data hold time Table 28 - SYS_IRQ Interface Timing Symbol TSU:DAT THD:IRQ THD:DATA Value 0 ns 150 ns 150 ns ATA/ATAPI Port Timing Characteristics All input signals on the ATA/ATAPI port are considered asynchronous, and are synchronized to the chip's internal system clock. All output signals are clocked using the chip's internal system clock, for which there is no external reference. Thus, the output signals should be considered asynchronous. The PIO mode used for data register accesses is retrieved from the device or specified in the ISD-300A1 configuration bytes. Clock Crystal Frequency Duty Cycle KDS AT-49 crystal, 10pf load capacitance. 30 MHz 0.005% n/a Note: Clock signal frequency is measured at VDD33/2 point. Rise and fall times should be 2 ns or less. Table 29 - Clock Requirements Reset The ISD-300A1 requires an off-chip power-on reset circuit. NRESET must be held asserted for a minimum of 1 ms after power is stable. 49 October 19, 2001 ISD-300A1 Physical Diagrams Figure 8 - Package Outline Diagram 50 October 19, 2001 ISD-300A1 Appendix A - Example EEPROM or FBh Identify Data Contents Address Field Name Description Example SROM Data ISD-300A1 Configuration Data 0x0 (Byte 0) 0x1 (Byte 1) 0x2 (Byte 0) 0x3 (Byte 1) I2C memory device Signature (lsb) I2C memory device Signature (msb) Event Notification APM Value lsb I2C memory device Signature byte. Register does not exist in HW msb I2C memory device Signature byte. Register does not exist in HW ATAPI event notification command. Setting this field to 0x00 disables this feature. Bit(7:0) ATA Device Automatic Power Management Value. If an attached ATA device supports APM and this field contains other than 0x00, the Initialization state machines will issue a SET FEATURES command to Enable APM with the register value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This register value is ignored with ATAPI devices. Time in 128 millisecond granularity before the ISD-300A1 stops polling the ALT STAT register for reset complete and restarts the reset process (0x80 = 16.4 seconds). 0x54 0x4D 0xFC 0x00 0x4 ATA Initialization Timeout 0x80 51 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0x5 USB Bus Mode Bit (7) - read only. USB bus mode of operation 0 USB bus is operating in full speed mode (12 Mbit/sec). 1 USB bus is operating in high speed mode (480 Mbit/sec). Bit (6) CBW Command Block Size. 0 12 byte ATAPI CB 1 16 byte ATAPI CB Bit (5) Device number selection. This bit is valid only when "Skip ATA/ATAPI Device Initialization" is active. Under ISD-300A1 control ("Skip ATA/ATAPI Device Initialization = `0'), the value is ignored. 0 Drive 0 (master) 1 Drive 1 (slave) Bit (4) ATAPI reset during drive initialization. Setting this bit enables the ATAPI reset algorithm in the drive initialization state machines Bit (3) - read only. Indicates if an ATA or ATAPI device is detected 0 ATAPI device 1 ATA device or possible device initialization failure. Bit(2) Force USB full speed only operation. Setting this bit prevents the ISD-300A1 from negotiating HS operation during USB reset events 0 Normal operation - allow HS negotiation during USB reset 1 USB FS only - do not allow HS negotiation during USB reset Bit(1) Vendor Specific / MSC SOFT_RESET control. 0 Vendor Specific USB command utilized for SOFT_RESET 1 Mass Storage Class USB command utilized for SOFT_RESET Bit (0) DISK_READY active polarity. DISK_READY Polarity is ignored if I_MODE is set to 1. During I_MODE operation DISK_READY polarity is active high. 0 Active high polarity 1 Active low polarity Value in CBW CB field that designates if the CB is decoded as vendor specific ATA commands instead of the ATAPI command block. Value in CBW CB field that designates if the CB is decoded as vendor specific ATA commands instead of the ATAPI command block. 0x00 ATAPI Command Block Size Master/Slave Selection ATAPI Reset ATA_NATAPI Force USB FS VS / MSC SOFT_RESET DISK_READY Polarity 0x6 0x7 ATA Command Designator (Byte 0, lsb) ATA Command Designator (Byte 1, msb) 0x24 0x24 52 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0x8 Initialization Status Bit (7) - read only Drive Initialization Status If set, indicates the drive initialization sequence state machine is active Bit (6) Allows software to manually enable ATA Translation with devices that do not support ISD-300A1 device initialization algorithms. Note: Force ATA Device must be set'1' in conjunction with Skip ATA/ATAPI Device Initialization and ATA Translation Enable. Software must issue an INQUIRY command followed with a MSC reset to allow the ISD-300A1 to parse drive information and optimize system performance and operation. Force ATA Device should be set `0' for devices that support ISD-300A1 device initialization algorithms. Bit (5) Skip_Init - This bit should be cleared for I_MODE operation. The host driver must initialize the attached device (if required) when this bit is set. Note:For ATAPI devices, if Skip_Init is set the host driver must issue an IDENTIFY command utilizing ATACBs to allow the ISD-300A1 to parse drive information to optimize system performance and operation. Refer to bmATACBActionSelect in the ATA Command Block - Field Descriptions section on page 30 for further information. 0 normal operation 1 only reset the device and write the device control register prior to processing commands. Bit (4:3) - Shall be set to `0' Bits (2:0) Maximum number of LUNs device supports. Bits (7) - read only. Current logic state of the ATA_EN pin Bit (6:1) - Should be set to 0 Bit (0) SRST reset during drive initialization. Setting this bit enables the SRST reset algorithm in the drive initialization state machines. Bits (7:4) Standard values for ATA compliant devices and a 30.0 MHz system clock (in binary). Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 0101 (5+1)*33.33 = 200 ns mode 1 0011 (3+1)*33.33 = 133 ns mode 2 0011 (3+1)*33.33 = 133 ns mode 3 0010 (2+1)*33.33 = 100 ns mode 4 0010 (2+1)*33.33 = 100 ns Bits (3:0) ATA cycle times are calculated using Data Assert and Data Recover values. Standard recover values and cycle times for ATA compliant devices and a 30.0 MHz system clock (in binary). Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 1100 (4+1)+(12+1)*33.33 = 600 ns mode 1 0111 (3+1)+(7+1)*33.33 = 400 ns mode 2 0011 (2+1)+(3+1)*33.33 = 233 ns mode 3 0010 (2+1)+(2+1)*33.33 = 200 ns mode 4 0000 (2+1)+(0+1)*33.33 = 133 ns 0x00 Force ATA Device Skip ATA / ATAPI Device Initialization Obsolete Last LUN Identifier 0x9 ATA_EN Obsolete SRST Enable 0xA ATA Data Assert 0x01 0x20 ATA Data Recover 53 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0xB ATA Data Setup Bits (7:5) Setup time is only incurred on the first data cycle of a burst. Standard values for ATA compliant devices and a 30.0 MHz system clock are (in binary): Note: These values are only valid when the Override PIO Timing configuration bit is set. mode 0 010 (2+1)*33.33 = 133 ns mode 1 001 (1+1)*33.33 = 66 ns mode 2 001 (1+1)*33.33 = 66 ns mode 3 001 (1+1)*33.33 = 66 ns mode 4 000 (0+1)*33.33 = 33 ns Bit (4) Controls the polarity of DRV_PWR_VALID pin 0 Active low ("connector ground" indication) 1 Active high (power indication from device) Bit (3) This field is used in conjunction with ATA Data Setup, ATA Data Assertion, ATA Data Recover, and PIO Mode Selection fields. 0 Use timing information acquired from the Drive 1 Override device timing information with configuration values Bit (2) Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be enabled in cable applications where the ISD-300A1 is VBUS powered. 0 pin disabled (most systems) 1 pin enabled Bit(1) PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data bus during PIO read operations while addressing the data register. In most applications this bit is set to `0'. This functionality is provided as a solution for devices that erroneously drive the ATA data bus continuously during PIO data register reads. 0 Normal operation as per ATA/ATAPI interface specification. 1 3-state (hi-Z) DD[15:0] during PIO data register reads. Bit (0) - read only This bit reflects the current state of the I_MODE input pin. 0x00 Drive Power Valid Polarity Override PIO Timing Drive Power Valid Enable ATA Read Kludge I_MODE 54 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0xC SYS_IRQ DISK_READY ATA Translation Enable Bits(7) - read only This bit reflects the current logic state of the SYS_IRQ input. Bit(6) - read only This bit reflects the current logic state of the DISK_READY input. Bit(5) Enable ATAPI to ATA protocol translation enable. If enabled, AND if an ATA device is detected, ATA translation is enabled. Note: If Skip ATA/ATAPI Device Initialization is set `1', Force ATA Device must also be set `1' in order to utilize ATA translation. Software must further issue an INQUIRY command followed with an MSC reset to enable ATA translation operation. 0 ATA Translation Disabled 1 ATA Translation Enable Bit(4) Enable Ultra Mode data transfer support for ATA devices. If enabled, AND the ATA device reports UDMA support, the ISD-300A1 will utilize UDMA data transfers. 0 Disable ATA device UDMA support 1 Enable ATA device UDMA support Bit(3) Enable Ultra Mode data transfer support for ATAPI devices. If enabled, AND the ATAPI device reports UDMA support, the ISD-300A1 will utilize UDMA data transfers. 0 Disable ATAPI device UDMA support 1 Enable ATAPI device UDMA support Bits(2:0) ROM UDMA Mode indicates the highest UDMA mode supported by the product. The ISD-300A1 will utilize the lesser of ROM UDMA Mode or the highest mode supported by the device. Note: UDMA read operation mode timing is controlled by the device. mode 0 000 133.3 ns per 16-bit word write mode 1 001 100 ns per 16-bit word write mode 2 010 66.7 ns per 16-bit word write mode 3 011 66.7 ns per 16-bit word write mode 4 100 33.3 ns per 16-bit word write 0x32 ATA UDMA Enable ATAPI UDMA Enable ROM UDMA Mode 55 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0xD PIO Mode Selection Bits (7:5) PIO Mode Selection. The PIO mode reported back to the device if the Override PIO Timing configuration bit is set. This field represents the PIO mode of operation configured by the ATA Data Setup, ATA Data Assertion, ATA Data Recover, and Override PIO Timing fields. mode 0 000 mode 1 001 mode 2 010 mode 3 011 mode 4 100 Bit (4) Skip ATA_NRESET assertion. Note: SRST Enable must be set in conjunction with Skip Pin Reset. Setting this bit causes the Initialize algorithm to bypass ATA_NRESET assertion unless a drive Power On Reset cycle occurred, utilizing SRST as the drive reset mechanism. . 0 Allow ATA_NRESET assertion 1 Disable ATA_NRESET assertion Bits (3:2) GPIO[9:8] input / output control Writing this register controls the output state of the GPIO pin (if the 3-state control is enabled) Reading this register returns the logic value from the GPIO pin Bits (1:0) GPIO[9:8] 3-state control 0 Output enabled (GPIO pin is an output) 1 3-state (hi-Z) (GPIO pin is an input) Bits(7:0) GPIO[7:0] input / output control Writing this register controls the output state of the GPIO pin (if the 3-state control is enabled) Reading this register returns the logic value from the GPIO pin Bits(7:0) GPIO[7:0] 3-state control 0 Output enabled (GPIO pin is an output) 1 3-state (hi-Z) (GPIO pin is an input) USB Device Descriptor Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. Device class. Device subclass. Device protocol. Maximum USB packet size supported Vendor ID. Product ID. Device release number in BCD lsb (product release number) Device release number in BCD msb (silicon release number). NOTE: This field entry is always returned from internal ROM contents, regardless of the descriptor source. Index to manufacturer string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. 0x23 Skip Pin Reset General Purpose IO General Purpose IO 3-state control 0xE General Purpose IO 0x00 0xF General Purpose IO 3-state control 0xFF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB) bcdDevice (MSB) iManufacturer 0x12 0x01 0x00 0x02 0x00 0x00 0x00 0x40 0xAB 0x05 0x60 0x00 0x00 0x10 0x49 56 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0x1F 0x20 iProduct iSerialNumber Index to product string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Index to serial number string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. The USB Mass Storage Class Bulk Only Transport Specification requires a unique serial number. Number of configurations supported. USB Device Qualifier Descriptor 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations bReserved bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes Device class. Device subclass. Device protocol. Maximum USB packet size supported Number of configurations supported Reserved for future use, must be zero USB Standard Configuration Descriptor 1 Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to the configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved. `1' 6 Self-powered. `1' 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' Maximum power consumption for this configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). USB Other Speed Configuration Descriptor 1 Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved. `1' 6 Self-powered. `1' 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' 0x09 0x02 0x27 0x00 0x01 0x02 0x00 0x80 Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. 0x0A 0x06 0x00 0x02 0x00 0x00 0x00 0x40 0x01 0x00 0x5A 0x6E 0x21 bNumConfigurations 0x01 0x34 bMaxPower 0xF9 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes 0x09 0x07 0x27 0x00 0x01 0x02 0x00 0x80 57 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0x3D bMaxPower Maximum power consumption for the second configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). USB Interface Descriptor (HS) Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings Number of endpoints Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or zero if the string does not exist. USB Bulk Out (HS) Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 1. This is a bulk endpoint. Max data transfer size. HS interval for polling (max NAK rate.) USB Bulk In (HS) 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval HS interval for polling (max NAK rate). Does not apply to FS bulk endpoints. USB Interrupt (HS) Length of this descriptor in bytes. Endpoint descriptor type. This is an Interrupt endpoint, endpoint number 3. This is an interrupt endpoint. Max data transfer size. This is the polling interval. 0x0A = 64ms. Unused I2C memory device / internal ROM space for address pointer alignment USB Interface Descriptor (FS) bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings Number of endpoints Interface class. Interface subclass. Interface protocol. Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. 0x07 0x05 0x82 0x02 0x00 0x02 0x01 0xF9 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface 0x09 0x04 0x00 0x00 0x03 0x08 0x06 0x50 0x00 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (lsb) wMaxPacketSize (msb) bInterval 0x07 0x05 0x01 0x02 0x00 0x02 0x01 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C bLength bDescriptorType bEndpointAddress BmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval 0x07 0x05 0x83 0x03 0x02 0x00 0x0A 0x00 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x09 0x04 0x00 0x00 0x03 0x08 0x06 0x50 58 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0x65 iInterface Index to first interface string. This entry must equal half of the address value where the string starts or zero if the string does not exist. USB Bulk Out (FS) Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 1. This is a bulk endpoint. Max data transfer size. Interval for polling USB Bulk In (FS) 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (lsb) wMaxPacketSize (msb) bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (lsb) wMaxPacketSize (msb) bInterval Bulk In descriptor length Descriptor type Endpoint address Attributes Max packet size lsb Max packet size msb Interval for polling USB Interrupt (FS) Interrupt descriptor length Descriptor type Endpoint address Attributes Max packet size lsb Max packet size msb Interval for polling Unused I2C memory device / internal ROM space for address pointer alignment USB String Descriptor (LANGID) bLength bDescriptorType LANGID (lsb) LANGID (msb) bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes LANGID descriptor length Descriptor type Language supported lsb Language supported msb USB Standard Configuration Descriptor 2 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to the configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved. `1' 6 Self-powered. `1' 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' Maximum power consumption for this configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). 0x09 0x02 0x27 0x00 0x01 0x02 0x00 0xC0 0x07 0x05 0x83 0x03 0x02 0x00 0x40 0x00 0x07 0x05 0x82 0x02 0x40 0x00 0x00 0x00 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (lsb) wMaxPacketSize (msb) bInterval 0x07 0x05 0x01 0x02 0x40 0x00 0x00 0x7C 0x7D 0x7E 0x7F 0x04 0x03 0x09 0x04 0x88 bMaxPower 0x0x31 59 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data USB Other Speed Configuration Descriptor 2 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration bmAttributes Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The ISD-300A1 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02 Index to configuration string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On-board default 7 Reserved. `1' 6 Self-powered. `1' 5 Remote wake-up. `0' 4-0 Reserved, set to 0. `0' Maximum power consumption for the second configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). USB String Descriptor (Manufacturer) Descriptor length Descriptor type ("I") ("NUL") ("n") ("NUL") ("-") ("NUL") ("S") ("NUL") ("y") ("NUL") ("s") ("NUL") ("t") ("NUL") ("e") ("NUL") ("m") ("NUL") (" ") ("NUL") ("D") ("NUL") ("e") ("NUL") ("s") ("NUL") ("i") ("NUL") ("g") 0x09 0x07 0x27 0x00 0x01 0x02 0x00 0xC0 0x91 bMaxPower 0x31 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString 0x22 0x03 0x49 0x00 0x6E 0x00 0x2D 0x00 0x53 0x00 0x79 0x00 0x73 0x00 0x74 0x00 0x65 0x00 0x6D 0x00 0x20 0x00 0x44 0x00 0x65 0x00 0x73 0x00 0x69 0x00 0x67 60 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD bString bString bString bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bLength bDescriptorType ("NUL") ("n") ("NUL") USB String Descriptor (Product) Descriptor length Descriptor type ("U") ("NUL") ("S") ("NUL") ("B") ("NUL") (" ") ("NUL") ("S") ("NUL") ("t") ("NUL") ("o") ("NUL") ("r") ("NUL") ("a") ("NUL") ("g") ("NUL") ("e") ("NUL") (" ") ("NUL") ("A") ("NUL") ("d") ("NUL") ("a") ("NUL") ("p") ("NUL") ("t") ("NUL") ("e") ("NUL") ("r") ("NUL") USB String Descriptor (Serial Number) Descriptor length Descriptor Type 0x24 0x03 0x28 0x03 0x55 0x00 0x53 0x00 0x42 0x00 0x20 0x00 0x53 0x00 0x74 0x00 0x6F 0x00 0x72 0x00 0x61 0x00 0x67 0x00 0x65 0x00 0x20 0x00 0x41 0x00 0x64 0x00 0x61 0x00 0x70 0x00 0x74 0x00 0x65 0x00 0x72 0x00 0x00 0x6E 0x00 61 October 19, 2001 ISD-300A1 Address Field Name Description Example SROM Data 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF 0x100 + bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString ("0") ("NUL") ("1") ("NUL") ("2") ("NUL") ("3") ("NUL") ("4") ("NUL") ("5") ("NUL") ("6") ("NUL") ("7") ("NUL") ("8") ("NUL") ("9") ("NUL") ("0") ("NUL") ("1") ("NUL") ("2") ("NUL") ("3") ("NUL") ("4") ("NUL") ("5") ("NUL") ("6") ("NUL") Unused I2C memory device space 0x30 0x00 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00 0x37 0x00 0x38 0x00 0x39 0x00 0x30 0x00 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00 0xXX Table 30 - Example I2C memory device / FBh Identify Data 62 |
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